Stacked Chip Package with Redistribution Layer
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Solution Overview
Problem
The existing chip packaging process is limited by the size of printed circuit boards, making it difficult to further miniaturize electronic products due to the independent and separate placement of chip packages, which restricts the integration of multiple integrated circuit functions.
Innovation Solution
A chip package design involving multiple device substrates stacked vertically, with an insulating layer and redistribution layer that includes bumps for electrical connections, allowing for the integration of various integrated circuit functions within a single package, reducing the size of the printed circuit board required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chip packages are separately and independently disposed on a printed circuit board, then electrical connection paths can be provided between electronic elements, but the size of the printed circuit board increases
Solution Approach 1:
The patent merges multiple chip packages into a single integrated package structure where first, second, and third device substrates are stacked and bonded together. The insulating layer integrates multiple packages, allowing electrical connections between electronic elements while reducing the overall footprint on the printed circuit board.
Solution Approach 2:
The patent transitions from a two-dimensional arrangement of separate chip packages on a printed circuit board to a three-dimensional stacked configuration. By bonding device substrates vertically (first surface to second surface), the design utilizes the vertical dimension to reduce the horizontal area occupied on the printed circuit board.
2Area of stationary object
If multiple chip packages are integrated in a single package, then the printed circuit board size is reduced, but the fabrication process becomes more complex
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming openings in the insulating layer, depositing conductive plugs in some openings, depositing conductive layers in other openings, and forming vias. This segmentation simplifies the overall fabrication by breaking down the complex integration process into manageable, sequential steps.
Solution Approach 2:
The patent applies different treatments to different regions of the insulating layer. Some openings receive conductive plugs, while other openings receive conductive layers, allowing for customized electrical connections in different areas of the integrated package based on specific functional requirements.
3Reliability
If through-silicon vias are used for electrical connections, then reliable electrical paths are achieved, but manufacturing costs and processing time increase
Solution Approach 1:
The patent extracts the electrical connection function from the traditional through-silicon via approach and implements it through openings formed in the insulating layer. These openings provide direct electrical pathways between stacked device substrates without requiring through-silicon via fabrication, thereby reducing processing time and costs while maintaining reliable electrical connections.
Data Source
AI summary
A chip package including a first device substrate is provided. The first device substrate is attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate opposite to the first surface. An insulating layer covers the first, second and third device substrates and has at least one opening therein. At least one bump is disposed under a bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected to the bump through the opening. A method for forming the chip package is also provided.