Semiconductor chip, semiconductor device, and semiconductor package including the semiconductor chip
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Solution Overview
Problem
Semiconductor packages face challenges in achieving improved adhesion reliability and heat dissipation while maintaining a thin and light design, particularly at the edges where semiconductor chips are mounted, due to limitations in current electrical connection and thermal management strategies.
Innovation Solution
The semiconductor package incorporates a design with varying height and width chip connection pads and redistribution structures, along with an adhesive layer and connection members, to enhance adhesion reliability and heat dissipation by optimizing the connection and thermal interface between stacked semiconductor chips, and uses a molding member and heat dissipating structures to manage heat effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor packages use a stacked structure with multiple chips to increase storage capacity, then the storage capacity increases, but the adhesion reliability at edges deteriorates
Solution Approach 1:
The patent applies local quality by making the second chip connection pad have different dimensions (greater height and width) compared to the first chip connection pad. This local differentiation specifically addresses the edge region where the second chip is mounted, providing enhanced adhesion reliability at the critical edge location without affecting the overall package structure or storage capacity.
2Length of moving object
If semiconductor packages are made thinner and lighter to meet design requirements, then the package size and weight decrease, but the heat dissipation performance deteriorates
Solution Approach 1:
The patent employs dimensionality change by extending the second chip connection pad in the vertical direction (greater height) to provide additional heat dissipation pathway. This allows the thin package to maintain effective thermal management by utilizing the vertical dimension for heat conduction from the second chip through the enlarged connection pad to the substrate, compensating for the reduced horizontal heat dissipation area.
3Reliability
If chip connection pads are enlarged to improve adhesion reliability, then the adhesion reliability improves, but the electrical connection structure complexity increases
Solution Approach 1:
The patent applies asymmetry by making the second chip connection pad asymmetrically larger than the first chip connection pad. Specifically, the second chip connection pad has greater height and width dimensions, creating an asymmetric structure that targets the specific adhesion needs at the second chip location while maintaining a relatively simple overall electrical connection structure that can be manufactured using standard processes.
Data Source
AI summary
A semiconductor chip including a semiconductor substrate having a first surface and a second surface and having an active layer in a region adjacent to the first surface, a first through electrode penetrating at least a portion of the semiconductor substrate and connected to the active layer, a second through electrode located at a greater radial location from the center of the semiconductor substrate than the first through electrode, penetrating at least a portion of the semiconductor substrate, and connected to the active layer. The semiconductor chip also including a first chip connection pad having a first height and a first width, located on the second surface of the semiconductor substrate, and connected to the first through electrode, and a second chip connection pad having a second height greater than the first height and a second width greater than the first width, located on the second surface of the semiconductor substrate, and connected to the second through electrode.