Stacked Chip SPAD Image Sensor High Fill-Factor
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Solution Overview
Problem
Conventional single-photon avalanche diode (SPAD) image sensors have a limited fill-factor due to the space occupied by counters and trade-offs between SPAD and transistor performance in traditional CMOS processes.
Innovation Solution
A stacked chip architecture is employed, where SPADs are formed on one chip and digital counters on another, allowing for high fill-factor SPAD arrays and optimized SPAD performance without compromising transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If counters are integrated on the same semiconductor substrate as SPAD regions, then the image sensor can be manufactured using traditional CMOS processes, but the fill-factor is limited due to space occupation by counters
Solution Approach 1:
The patent divides the image sensor into two separate chips: a first chip containing only SPAD regions and a second chip containing digital counters and readout circuitry. This segmentation allows each chip to be optimized independently, achieving high fill-factor on the SPAD chip while maintaining manufacturability through separate fabrication processes.
Solution Approach 2:
The patent transitions from a planar integration approach to a three-dimensional stacked architecture. By stacking the SPAD chip and counter chip vertically and connecting them through wafer-level bonding and through-silicon vias, the solution moves counter components to another spatial dimension, eliminating their area occupation on the SPAD sensing plane.
2Ease of manufacture
If SPADs and transistors are fabricated in the same traditional CMOS process, then manufacturing is simplified, but trade-offs must be made between SPAD performance and transistor performance
Solution Approach 1:
The patent separates the fabrication processes for SPAD regions and transistor-based circuitry into different chips. The first chip with SPAD regions can be fabricated using specialized processes optimized for photon detection, while the second chip with counters uses standard CMOS processes, eliminating performance trade-offs.
Solution Approach 2:
The patent applies different fabrication qualities and processes to different functional regions. The SPAD chip uses processes optimized for high quantum efficiency and low noise, while the counter chip uses standard CMOS processes optimized for digital logic performance, allowing each region to have its own optimal fabrication quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stacked chip structure achieves a very high fill-factor for SPAD arrays, enabling high-speed and low-light-sensitive imaging with improved SPAD performance and reduced space occupation by counters.
Implementation Method 1
A SPAD (also referred to as a Geiger-mode avalanche photodiode (G-APD)) is a solid-state photodetector capable of detecting a low intensity signal, such as low as a single photon
Implementation Method 2
The SPAD regions have a p-n junction that is reverse biased above the breakdown voltage such that a single photo-generated carrier can trigger an avalanche multiplication process
Data Source
AI summary
An example imaging sensor system includes a Single-Photon Avalanche Diode (SPAD) imaging array formed in a first semiconductor layer of a first wafer. The SPAD imaging array includes an N number of pixels, each including a SPAD region formed in a front side of the first semiconductor layer. The first wafer is bonded to a second wafer at a bonding interface between a first interconnect layer of the first wafer and the second interconnect layer of the second wafer. An N number of digital counters are formed in a second semiconductor layer of the second wafer. Each of the digital counters are configured to count output pulses generated by a respective SPAD region.