Stacked Semiconductor Chip Logic for TSV Leakage Suppression
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Solution Overview
Problem
In semiconductor devices with stacked chips, maintaining all through vias at a low level during the stand-by state to suppress leakage current is challenging, especially when some terminals need to receive signals of different logic levels, which prevents uniform control of leakage current.
Innovation Solution
The implementation of a semiconductor device structure where through vias are managed using AND gates and logic gates, including inverter circuits, to ensure that all terminals are fixed to the same logic level during the stand-by state, preventing leakage current by disabling the CSID circuit and using latch circuits to store CSID bits, allowing signals to be inverted appropriately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If all TSVs are fixed to the low level during stand-by state, then leakage current is suppressed, but terminals cannot receive signals of different logic levels
Solution Approach 1:
The patent implements dynamic control of TSV potential levels by using control signals to switch between stand-by mode (all TSVs at low level to suppress leakage) and operation mode (specific TSVs can be at high level to receive different logic signals). This dynamic switching resolves the contradiction between leakage suppression and signal reception versatility.
Solution Approach 2:
The patent applies different potential levels to different TSVs based on their specific function and location. During operation, while most TSVs remain at low level, specific TSVs connected to terminals requiring different logic levels are selectively raised to high level. This local differentiation maintains leakage suppression overall while enabling necessary signal reception at specific locations.
2Adaptability or versatility
If TSVs are allowed at different potential levels for signal reception, then terminal signal capability is improved, but leakage current increases during stand-by state
Solution Approach 1:
The control circuit dynamically adjusts TSV potential levels based on operational state. During stand-by, all TSVs are held at low level to minimize leakage. When signal reception is needed, the control circuit selectively raises specific TSVs to high level only for the duration and locations required, then returns them to low level, thus minimizing overall leakage while maintaining signal capability when needed.
3Object-generated harmful factors
If control circuits are added to manage TSV logic levels, then leakage current is suppressed, but device complexity increases
Solution Approach 1:
The control circuit is designed to perform multiple functions: it manages stand-by mode for all TSVs, handles operation mode for specific TSVs, and coordinates with terminal signal reception requirements. By making the control circuit multi-functional, the patent reduces the need for separate dedicated circuits for each function, thereby suppressing leakage current while limiting the increase in overall device complexity.
Data Source
AI summary
A semiconductor device of one embodiment includes semiconductor chips. While the semiconductor device is receiving a power supply and a chip enable signal which is negated, all external terminals of the semiconductor chips are at the same logic level.