Stacked Chip Wiring Lines With Variable Bonding Portions
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Solution Overview
Problem
Existing semiconductor devices with stacked chips lack efficient utilization of bonding portions for optimal wiring performance, leading to suboptimal reliability and characteristics in inter-chip connections.
Innovation Solution
The implementation of multiple types of wiring lines with varying numbers of contacts and bonding portions in the overlap area between stacked chips, allowing for optimized ratios and configurations to enhance reliability and reduce parasitic capacitance, thereby improving inter-chip wiring efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple types of wiring lines with varying numbers of bonding portions are implemented, then reliability of inter-chip connections is improved, but device complexity increases
Solution Approach 1:
The wiring lines are segmented into multiple types based on the number of bonding portions they contain. First wiring lines have a first number of bonding portions while second wiring lines have a second number of bonding portions, allowing the inter-chip connection system to be divided into different reliability categories for different signal requirements
Solution Approach 2:
Different wiring lines are assigned different numbers of bonding portions based on their specific functional requirements. Critical signals use wiring lines with more bonding portions for higher reliability, while less critical signals use wiring lines with fewer bonding portions, optimizing the overall system without uniform complexity
2Reliability
If the number of bonding portions in wiring lines is increased, then reliability is improved, but parasitic capacitance increases
Solution Approach 1:
The patent changes the parameter of bonding portion count to create different wiring line types. By varying this discrete parameter, the system achieves different reliability levels while managing parasitic capacitance through selective application to different signal types
3Productivity
If wiring lines with optimized ratios of contacts to bonding portions are used, then inter-chip wiring efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The conductive patterns are pre-configured with specific numbers of bonding portions during the chip fabrication process. This preliminary action allows for optimized wiring line types to be built-in before stacking, reducing the precision requirements during the bonding process itself
Data Source
AI summary
A semiconductor device in which a first chip and a second chip are stacked including a first wiring line and a second wiring line by which the first chip and the second chip are electrically connected. The first wiring line and the second wiring line each include a bonding portion for bonding one of a plurality of conductive patterns placed in the first chip and one of a plurality of conductive patterns placed in the second chip. The number of bonding portions included in the first wiring line is larger than the number of bonding portions included in the second wiring line.