Stacked Semiconductor Chip Voltage Control via Internal Wiring
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Solution Overview
Problem
Existing semiconductor devices require a large mounting area when stacking multiple chips due to the need for separate packages and lack a stable method for operating regulator circuits in a stacked configuration, particularly in reducing noise from signal transmission and reception between chips.
Innovation Solution
A semiconductor device design where two chips are stacked within the same package, with a regulator circuit generating internal power supply voltage and a monitor pad connected to a coupling path between the chips, reducing noise influence through optimized pad placement and wiring connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two semiconductor chips are accommodated in different packages, then each chip can be supplied with power supply voltages via external terminals, but the mounting area becomes considerably large
Solution Approach 1:
The patent combines two previously separate packages into a single multi-chip package. The first semiconductor chip (regulator chip) and second semiconductor chip (load chip) are mounted on the same package substrate, allowing power supply voltages to be delivered internally through the package rather than requiring separate external packages. This merging reduces the overall mounting area while maintaining reliable power delivery.
Solution Approach 2:
The patent transitions from a two-dimensional side-by-side package arrangement to a three-dimensional multi-chip stack within a single package. By stacking chips vertically on the same package substrate and using internal wiring layers, the solution reduces the footprint area while maintaining power delivery capability through vertical interconnections.
2Area of stationary object
If two chips are mounted in the same plane in one package, then the mounting area is reduced, but the regulator circuit operation becomes unstable
Solution Approach 1:
The patent segments the power supply voltage delivery path into separate internal wiring layers within the package. The power supply voltage input terminal is electrically connected to the regulator circuit through dedicated internal wiring, which is further connected to the load chip. This segmentation isolates the regulator circuit from noise and interference, ensuring stable operation while maintaining compact mounting.
Solution Approach 2:
The patent introduces internal wiring layers as intermediaries between the power supply voltage input terminal and the chips. These internal wiring structures act as controlled impedance paths that stabilize voltage delivery and reduce noise coupling, enabling stable regulator circuit operation in the compact multi-chip configuration.
3Productivity
If signal transmission and reception occur between stacked chips, then integration is achieved, but noise interference increases
Solution Approach 1:
The patent segments signal and power pathways into separate internal wiring layers. Signal transmission between chips occurs through dedicated signal wiring layers, while power supply voltages are delivered through separate power wiring layers. This segmentation prevents noise coupling between power and signal lines, reducing interference while maintaining efficient signal transmission.
Solution Approach 2:
The patent applies different wiring characteristics to different functional areas. Power supply wiring is designed with low impedance for stable voltage delivery, while signal wiring is optimized for high-frequency performance with appropriate impedance control. This local optimization of wiring quality reduces noise interference and improves signal integrity in the stacked chip configuration.
Data Source
AI summary
A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires, respectively. In another example, fourth and fifth pads are disposed along a side different from a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips.