Stacked Semiconductor Chip Internal Voltage Testing via Through-Chip Vias
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Solution Overview
Problem
In semiconductor integrated circuits with stack package structures, internal voltages generated by stacked semiconductor chips cannot be effectively tested after packaging due to the exposure of only the lowermost chip's pads, leading to potential defects during the stack packaging process.
Innovation Solution
A semiconductor integrated circuit design that includes a monitoring unit in the master chip to test internal voltages of slave chips through through-chip vias, with a method involving an internal voltage select signal, comparison unit, and path selection units to enable external testing of internal voltages after packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor chips are stacked vertically to increase memory capacity and mounting density, then the memory capacity and mounting efficiency are improved, but the internal voltages of stacked chips become inaccessible for testing
Solution Approach 1:
The patent introduces a new vertical dimension for testing by routing test signals through the TCV structure. Instead of accessing pads on the top surface (horizontal dimension), the testing is performed by applying test signals to pads on the bottom surface and routing them vertically through TCVs to reach internal voltage nodes of upper chips. This dimensional approach allows testing of stacked chip internal voltages without increasing footprint area.
Solution Approach 2:
The patent uses TCVs as intermediary structures to bridge the gap between accessible external pads and inaccessible internal voltage nodes. The TCVs serve as conductive pathways that transmit test signals from the bottom surface pads through intermediate chips to reach the internal voltage generation nodes of upper stacked chips, enabling indirect measurement of internal voltages.
2Reliability
If through-chip vias (TCVs) are used to electrically couple stacked semiconductor chips, then the physical and electrical connection between chips is improved, but the complexity of the package structure increases
Solution Approach 1:
The patent makes TCVs serve multiple functions: they provide mechanical support for stacking, establish electrical connections between chips for normal operation, and simultaneously serve as test signal pathways for measuring internal voltages. This multi-functionality reduces the need for separate test structures and minimizes overall package complexity despite the vertical stacking arrangement.
3Manufacturing precision
If individual semiconductor chips are tested before packaging, then the quality state can be checked, but defects occurring during the stack packaging process cannot be detected
Solution Approach 1:
The patent incorporates test structures (pads and TCV pathways) during the packaging process itself, enabling testing to be performed after stacking is complete. This preliminary preparation of test access structures allows for post-packaging testing of internal voltages, detecting defects that occur during the stacking process such as TCV connection issues or voltage generation problems in upper chips.
Data Source
AI summary
A semiconductor integrated circuit includes at least one second semiconductor chip configured to generate an internal voltage, and a first semiconductor chip including a monitoring unit configured to monitor the internal voltage, and a first pad configured to provide monitoring result information outputted from the monitoring unit to a test device.