Stacked CMOS Image Sensor MIM Capacitor Layout
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Solution Overview
Problem
The design and formation of metal-insulator-metal (MIM) capacitors in stacked complementary metal oxide semiconductor (CMOS) image sensors are hindered by the presence of additional structures in interlayer insulating layers, making it difficult to achieve large sizes and optimal layout freedom due to the thinness of these layers.
Innovation Solution
The MIM capacitor is formed in a contact pad insulating layer, which is thicker and has fewer structures, allowing for easier formation of larger capacitors and increased layout freedom, with copper (Cu) pads used for bonding between semiconductor chips to facilitate electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If MIM capacitors are formed in interlayer insulating layers, then electrical connections are established, but the thinness of these layers and presence of additional structures make it difficult to achieve large sizes and optimal layout freedom
Solution Approach 1:
The patent moves the MIM capacitor formation from the interlayer insulating layer space to the contact pad insulating layer, effectively changing the spatial dimension and location where capacitors are formed. This allows capacitors to be created in a thicker insulating layer with fewer structural constraints, enabling larger capacitor sizes and improved layout freedom while maintaining electrical connection functionality
Solution Approach 2:
The patent utilizes the existing contact pad insulating layer structure, which is already present in the CMOS image sensor manufacturing process, to host MIM capacitors. This approach repurposes an existing structural element for a dual function (both as pad insulation and capacitor substrate), simplifying the manufacturing process by eliminating the need for separate capacitor formation layers
2Adaptability or versatility
If contact pad insulating layer is used for MIM capacitor formation, then layout freedom and capacitor size are improved, but additional bonding structures are required between semiconductor chips
Solution Approach 1:
The patent makes the contact pad insulating layer serve multiple functions: it provides electrical insulation for the metal pads and simultaneously serves as the substrate for forming MIM capacitors. This multi-functionality eliminates the need for separate capacitor formation layers and reduces overall device complexity despite the enhanced layout freedom and capacitor size capabilities
Solution Approach 2:
The patent merges the capacitor formation process with the existing pad structure formation. By integrating MIM capacitor creation into the contact pad insulating layer formation sequence, the patent combines what would traditionally be separate manufacturing steps into a unified process, reducing complexity while achieving greater layout flexibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, improves process efficiency, and enhances mass productivity by allowing for easier integration of MIM capacitors with improved performance in CMOS image sensors.
Implementation Method 1
the first semiconductor chip is coupled to the second semiconductor chip through a connection between a first metal pad in a first pad insulating layer in a lowermost portion of the first wiring layer and a second metal pad in a second pad insulating layer in an uppermost portion of the second wiring layer
Data Source
AI summary
A stacked complementary metal oxide semiconductor (CMOS) image sensor includes: a first semiconductor chip in which a plurality of pixels are in an upper area in a two-dimensional array structure and a first wiring layer is in a lower area; and a second semiconductor chip in which a second wiring layer is arranged in an upper area and logic elements are in a lower area, wherein the first semiconductor chip is coupled to the second semiconductor chip through a connection between a first metal pad in a first pad insulating layer in a lowermost portion of the first wiring layer and a second metal pad in a second pad insulating layer in an uppermost portion of the second wiring layer, and wherein a metal-insulator-metal (MIM) capacitor is in at least one of the first pad insulating layer and the second pad insulating layer.