Stacked III-V and IV Composite Switch Parasitic Reduction
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Solution Overview
Problem
Conventional methods for combining III-Nitride transistors with silicon FETs in high power and high performance circuit applications often increase parasitic inductance and resistance, compromising the benefits of III-Nitride transistors by using a side-by-side configuration on a common support surface.
Innovation Solution
A composite switch design that cascades a high-voltage III-Nitride power transistor with a low-voltage or mid-voltage silicon transistor, configured in a stacked configuration to reduce parasitic inductance and resistance, and enhance thermal dissipation, using through-semiconductor vias for electrical coupling and direct mechanical contact between transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a side-by-side configuration is used to combine III-Nitride transistors with silicon FETs on a common support surface, then the devices can be integrated, but parasitic inductance and resistance increase
Solution Approach 1:
The patent transitions from a planar side-by-side configuration to a vertical stacked configuration, moving the integration approach to another dimension. The III-Nitride transistor is positioned directly above the silicon FET, with electrical coupling achieved through vertical interconnects (vias) through the substrate, thereby reducing current path length and parasitic inductance while maintaining integration
2Ease of manufacture
If a side-by-side configuration is used to combine III-Nitride transistors with silicon FETs, then the devices can be integrated, but thermal dissipation is compromised
Solution Approach 1:
The vertical stacking arrangement optimizes thermal management by enabling direct thermal coupling between the III-Nitride transistor and silicon FET through the substrate. Heat can dissipate more efficiently through the vertical path, and the compact stacked geometry improves heat sink utilization compared to extended planar layouts
3Object-affected harmful factors
If a stacked configuration is used to cascade III-Nitride transistor with silicon FET, then parasitic inductance and resistance are reduced, but device complexity increases
Solution Approach 1:
The patent merges the III-Nitride transistor and silicon FET into a single integrated vertical structure, combining multiple device functions in one compact package. The shared substrate and integrated interconnect structure reduce the number of separate components and connections needed, simplifying the overall system despite the vertical arrangement
Data Source
Figure 1
Figure 2A~2B
Figure 2C
AI summary
In one implementation, a group III-V and group IV composite switch includes a group IV transistor in a lower active die, the group IV transistor having a source and a gate situated on a bottom side of the lower active die. The group III-V and group IV composite switch also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a drain of the group IV transistor using a through-semiconductor via (TSV) of the upper active die.