Stacked Device Conductive Path Testing via Interface Circuit
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Solution Overview
Problem
Conventional boundary scan circuitry in stacked electronic devices increases device area, test time, power consumption, and loading on conductive paths, and fails to efficiently determine the continuity of conductive paths, leading to potential defects such as high resistance, gaps, or short circuits.
Innovation Solution
A method and apparatus that determine the continuity of conductive paths using an interface circuit unit and transistors to electrically couple conductive paths to supply nodes, applying test patterns to identify defects and potentially repair them, without relying on boundary scan circuitry, thereby reducing device area, power consumption, and test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional boundary scan circuitry is used to test conductive paths, then testing capability is provided, but device area increases, test time increases, power consumption increases, and loading on conductive paths increases
Solution Approach 1:
The patent extracts the testing function from conventional boundary scan circuitry and implements it using a simplified interface circuit unit with transistors that selectively couple conductive paths to supply nodes. This extraction removes the need for complex boundary scan logic while retaining the essential testing capability, thereby reducing device area and power consumption.
Solution Approach 2:
The patent introduces an interface circuit unit with transistors as an intermediary between the conductive paths and supply nodes. This intermediary enables selective electrical coupling for testing purposes without requiring full boundary scan circuitry, thus providing testing capability with reduced area, power, and loading overhead.
2Reliability
If conventional boundary scan circuitry is used to test conductive paths, then testing capability is provided, but test time increases
Solution Approach 1:
The patent segments the testing process by using transistors to selectively couple individual conductive paths or groups of conductive paths to supply nodes in a controlled manner. This segmentation allows for efficient sequential testing without the overhead of conventional boundary scan operations, thereby reducing test time while maintaining testing capability.
3Reliability
If conventional boundary scan circuitry is used to test conductive paths, then testing capability is provided, but power consumption increases
Solution Approach 1:
The patent extracts only the essential testing function from conventional boundary scan circuitry, implementing it with a minimal interface circuit unit that uses transistors for selective coupling. This extraction eliminates the power-consuming boundary scan logic while preserving the core testing capability, thus reducing power consumption.
4Reliability
If conventional boundary scan circuitry is used to test conductive paths, then testing capability is provided, but loading on conductive paths increases
Solution Approach 1:
The patent introduces an interface circuit unit with transistors as an intermediary that provides controlled electrical coupling between conductive paths and supply nodes. This intermediary structure minimizes direct loading on the conductive paths compared to conventional boundary scan circuitry, as the transistors act as high-impedance switches that only engage during testing operations.
Data Source
AI summary
Various embodiments include apparatus and methods having circuitry to test continuity of conductive paths coupled to dice arranged in a stack. In at least one of these embodiments, a method includes electrically coupling each of the conductive paths to at least one of a first supply node and a second supply node. One of the conductive paths includes conductive material inside a via that can extend at least partly through a die among the dice in the stack. The method also includes receiving signals from the conductive paths, and determining continuity of the conductive paths based on the signals without using a boundary scan.


