Stacked Contact Plug Interconnection Layout for Semiconductor Devices
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Solution Overview
Problem
As semiconductor devices are downscaled, the reduced distances between interconnection lines and increased number of interconnections lead to difficulties in processing, increased interconnection resistance, and performance deterioration due to design restrictions, making it challenging to further downscale devices while maintaining reliability and yield.
Innovation Solution
The semiconductor device employs an interconnection layout with stacked contact plugs and varying width interconnections, where third and fourth interconnections are alternately disposed at different levels, connected by first and second contact plugs, respectively, to reduce resistance and prevent electrical shorts, allowing for increased integration density and reduced volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If interconnection lines are spaced closer together to increase integration density, then device area is reduced, but processing difficulty increases and reliability deteriorates
Solution Approach 1:
The patent introduces a third dimension by forming contact plugs at different vertical levels (first level and second level) to connect interconnection lines. This multi-level contact plug structure allows interconnection lines to be spaced closer horizontally while maintaining reliable electrical connections through vertically stacked contact plugs, thereby increasing integration density without sacrificing processing reliability
Solution Approach 2:
The patent employs nested contact plugs where a first contact plug is positioned inside or adjacent to a second contact plug at a different vertical level. This nesting arrangement allows multiple electrical connections to be made within a compact footprint, enabling closer spacing of interconnection lines while maintaining signal integrity and processing reliability
2Area of stationary object
If interconnection line width is reduced to increase integration density, then device area is reduced, but interconnection resistance increases
Solution Approach 1:
The patent compensates for reduced interconnection line width by adding vertical dimension through multi-level contact plugs. The stacked contact plug structure provides additional parallel conduction paths and reduces overall resistance by distributing current through multiple connection points, allowing thinner interconnection lines without increasing resistance
Solution Approach 2:
The patent merges multiple contact plugs into a stacked configuration where first and second contact plugs are positioned at different vertical levels. This combining of multiple connection paths in parallel reduces the effective resistance by providing multiple conduits for current flow, offsetting the resistance increase that would result from narrower interconnection lines
3Productivity
If number of interconnection lines is increased to increase integration density, then device functionality is improved, but processing difficulty increases
Solution Approach 1:
The patent resolves processing complexity by organizing multiple interconnection lines into a multi-level structure with contact plugs at different vertical positions. This three-dimensional arrangement allows a high number of interconnection lines to be managed systematically through standardized stacking patterns, making manufacturing more controllable despite increased density
Solution Approach 2:
The patent segments the interconnection structure into distinct horizontal layers with contact plugs connecting them vertically. This segmentation allows each layer to be processed and patterned independently, simplifying the manufacturing of complex multi-line interconnection structures by breaking them down into manageable sequential steps
Data Source
AI summary
A semiconductor device, which may be included in a display driver integrated circuit (IC) and a display device, includes a first interconnection and a second interconnection extending on a substrate and separate from each other, a third interconnection extending at a first level that is higher than a level at which the first interconnection and the second interconnection are disposed, and a fourth interconnection extending at a second level that is higher than the first level. A first contact plug is configured to connect the first interconnection and the third interconnection to each other. A stacked contact plug includes a second contact plug and a third contact plug, wherein the second contact plug is connected to the second interconnection, and the third contact plug is connected to the second contact plug and the fourth interconnection.