Stacked Decoupling Capacitors in Substrate for Low Inductance

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Solution Overview

Problem

Integrated circuit packages face challenges with parasitic loop inductance in power distribution networks, leading to increased output impedance and delayed transient responses due to the distance between voltage regulators and ICs, which is exacerbated by the miniaturization of transistors and the limited space for decoupling capacitors.

Innovation Solution

An integrated circuit package design that includes a land-side capacitor electrically coupled to a capacitor embedded in the package substrate, serving as decoupling capacitors to reduce loop inductance and improve transient response by providing a local power supply and efficient electrical coupling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If decoupling capacitors are placed close to the IC, then transient response is improved and loop inductance is reduced, but substrate area is consumed that could be used for other circuitry

Engineering Contradiction:
Improvetransient responseVSAvoidsubstrate area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extends the decoupling capacitor structure into the vertical dimension by creating stacked capacitors that occupy multiple layers of the substrate. The first capacitor is formed in a first region and the second capacitor is formed in a second region above the first region, allowing both capacitors to be electrically connected in parallel while occupying minimal planar area. This three-dimensional arrangement provides sufficient decoupling capacitance without consuming excessive substrate area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested capacitor structures where the second capacitor is positioned above and overlaps with the first capacitor in the vertical dimension. The electrodes and dielectric layers are arranged such that the second capacitor is effectively nested within the vertical space occupied by the first capacitor, maximizing space utilization and providing high capacitance density.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Productivity

If transistor size is reduced to increase density, then transistor density is improved, but space for decoupling capacitors is reduced

Engineering Contradiction:
Improvetransistor densityVSAvoidspace for decoupling capacitors
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent resolves this contradiction by moving the decoupling capacitor implementation from a two-dimensional planar arrangement to a three-dimensional stacked arrangement. Multiple capacitor layers are formed vertically, allowing high capacitance values to be achieved without increasing planar footprint. This enables continued transistor miniaturization while maintaining adequate decoupling capacitance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent combines multiple capacitor structures into a unified stacked decoupling system where the first and second capacitors are electrically connected in parallel. This merged structure provides the total decoupling capacitance required while occupying minimal substrate area, allowing maximum space for high-density transistor implementation.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If voltage regulator is placed far from IC, then layout flexibility is improved, but response time increases and power supply stability deteriorates

Engineering Contradiction:
Improvelayout flexibilityVSAvoidpower supply stability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent places decoupling capacitors in close proximity to the IC power supply pins, effectively pre-positioning charge reservoirs where they are most needed. These capacitors provide immediate charge during transient conditions, compensating for the longer response time of the remote voltage regulator and maintaining power supply stability despite the increased distance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The stacked decoupling capacitors act as intermediary elements between the remote voltage regulator and the IC. They provide a local charge reservoir that mediates the power supply connection, allowing the voltage regulator to be placed flexibly in the layout while the capacitors ensure stable power delivery to the IC by providing instantaneous charge during transients.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The arrangement of land-side and embedded capacitors reduces output impedance and enhances transient response, eliminating or minimizing parasitic loop inductance, thereby improving the electrical performance of the IC package.

Implementation Method 1

Decoupling capacitors provide additional stability to the power supplied to the IC. For instance, decoupling capacitors may reduce IC electrical impedance to ground for high-frequency transients and enable the IC to maintain a near-constant voltage across all operating frequencies.

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

Decoupling capacitors may reduce IC electrical impedance to ground for high-frequency transients and enable the IC to maintain a near-constant voltage across all operating frequencies.

Methodology Applied
Scientific EffectElectrical impedance reduction: Electrical Resistance

Data Source

PatentUS11417637B2Stacked decoupling capacitors with integration in a substrate
Publication Date: 2022.08.16 QUALCOMM INC
  • US11417637B2 patent drawing
  • US11417637B2 patent drawing
  • US11417637B2 patent drawing

AI summary

Certain aspects of the present disclosure generally relate to an integrated circuit package having a land-side capacitor electrically coupled to an embedded capacitor. One example integrated circuit package generally includes a package substrate having a first capacitor embedded therein, a semiconductor die disposed above the package substrate, and a second capacitor disposed below the package substrate and electrically coupled to the first capacitor.