3D Stacked Die Test Architecture for At-Speed TAP Operations
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Solution Overview
Problem
Existing test architectures for integrated circuit die are limited in their ability to efficiently support both individual die testing and final stacked die assembly testing, particularly due to limitations in TSM state transitions that prevent at-speed shift, capture, and update operations.
Innovation Solution
A test architecture that incorporates an improved TAP with a dual port router (DPR) and parallel test input/output mechanisms, allowing for seamless testing of functional circuits within the die, including capture, shift, and update operations without dead states, and supports both individual die and stacked die assembly testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional TAP architecture is used, then device complexity is reduced, but testing capability is limited and cannot support both individual die testing and stacked die assembly testing
Solution Approach 1:
The test architecture implements a universal test interface that can perform both individual die testing and stacked die assembly testing through the same TAP and DPR structure. The dual port router enables the system to adapt between different test modes (individual die test and stacked die test) by reconfiguring the signal paths, allowing one test architecture to serve multiple testing purposes without requiring separate dedicated test circuits for each function.
Solution Approach 2:
The test architecture segments the testing function into two distinct operational modes handled by the dual port router: individual die testing mode and stacked die assembly testing mode. The DPR can selectively route test signals to different destinations based on the test mode, effectively dividing the testing capability into separable functional segments that can be independently controlled while sharing the same physical infrastructure.
2Productivity
If TSM state transitions are used with dead states, then device complexity is minimized, but productivity is reduced due to inability to perform at-speed shift, capture, and update operations
Solution Approach 1:
The test architecture introduces dynamic control over TSM state transitions through the dual port router, which can selectively enable or disable certain state transitions based on the test mode. In at-speed testing mode, the DPR configures the TSM to perform shift, capture, and update operations in a single continuous sequence without dead states. In traditional mode, the DPR allows standard TSM operation with dead states, providing dynamic adaptability between different operational requirements.
Solution Approach 2:
The architecture eliminates dead states in the TSM state transitions by using the dual port router to create continuous signal paths that maintain uninterrupted test data flow. The DPR ensures that shift, capture, and update operations can occur in continuous succession without idle states, maintaining continuous useful action throughout the testing process and enabling at-speed operation.
3Loss of time
If individual die testing and stacked die assembly testing are supported separately, then measurement precision is maintained, but loss of time increases due to separate testing processes
Solution Approach 1:
The test architecture merges individual die testing and stacked die assembly testing into a single integrated test system. The dual port router enables both test functions to share the same TAP, signal paths, and control logic, combining what would traditionally require separate testing processes into one unified architecture that can switch between functions without requiring separate dedicated test equipment.
Solution Approach 2:
The unified test architecture provides universal testing capability that handles both individual die testing and stacked die assembly testing through the same infrastructure. The DPR enables the system to adapt between different test scenarios, allowing the test process to be performed once with mode switching rather than requiring separate testing procedures, thereby reducing total testing time while maintaining the complexity management through standardized interfaces.
Data Source
AI summary
This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.