Stacked Semiconductor Die Package with Cavity Substrate
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Solution Overview
Problem
The challenge in packaging semiconductor devices is to reduce the size of die packages while increasing functional capacity without increasing the surface area, which is complicated by the stacking of multiple dies that leads to higher failure probabilities and costs due to increased vertical profile and heat trapping.
Innovation Solution
The solution involves creating a stacked semiconductor die package with a substrate having cavities where the first die is mounted within the cavity and the second die is positioned over it, allowing for a thinner assembly, efficient heat dissipation, and reduced manufacturing costs by using air gaps between the dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor dies are stacked vertically to increase functional capacity without increasing surface area, then the processing power per package is improved, but the vertical profile increases requiring substantial die thinning and the probability of device failure increases
Solution Approach 1:
The patent transitions from planar die arrangement to three-dimensional stacking by positioning dies at different vertical levels within a package cavity. Multiple dies are arranged in a stacked configuration along the vertical dimension, allowing increased functional capacity without increasing the package footprint. This dimensional change enables higher density while maintaining reliability through proper spatial separation and thermal management.
2Area of stationary object
If multiple semiconductor dies are stacked vertically to reduce package footprint, then the surface area is reduced, but the vertical profile increases requiring substantial die thinning
Solution Approach 1:
The patent implements a nested arrangement where multiple semiconductor dies are positioned within a package cavity in a stacked configuration. Each die is placed within the vertical space of the package, with dies nested relative to one another along the vertical axis. This nesting approach maximizes the use of three-dimensional space, reducing the package footprint while managing the vertical profile through optimized die placement and cavity design.
3Quantity of substance
If multiple semiconductor dies are stacked vertically to increase processing power, then the functional capacity is improved, but heat trapping increases leading to higher operating temperatures
Solution Approach 1:
The patent extracts heat from the stacked die configuration by implementing thermal management structures that conduct heat away from the dies. Thermal vias, heat sinks, or heat spreaders are integrated into the package to extract heat generated by the stacked dies and dissipate it to the package exterior. This extraction approach enables high processing power while maintaining acceptable operating temperatures by preventing heat accumulation in the stacked die structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in higher yields, more efficient manufacturing, decreased costs, and lower operating temperatures due to improved heat management and reduced thermal effects on the dies.
Implementation Method 1
efficient heat dissipation
Implementation Method 2
improved heat management and reduced thermal effects on the dies
Data Source
AI summary
Integrated semiconductor assemblies and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device assembly comprises a base substrate having a cavity and a perimeter region at least partially surrounding the cavity. The cavity is defined by sidewalls extending at least partially through the substrate. The assembly further comprises a first die attached to the base substrate at the cavity, and a second die over at least a portion of the first die and attached to the base substrate at the perimeter region. In some embodiments, the first and second dies can be electrically coupled to each other via circuitry of the substrate.