Stacked Semiconductor Die for Parallel System-Level ESD Protection
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Solution Overview
Problem
Semiconductor devices are vulnerable to damage from electrostatic discharge (ESD), electrical over-stress (EOS), and electrical fast transients (EFT), and existing protection circuits have limited capability, leading to the need for larger package sizes which contradicts the goal of miniaturization.
Innovation Solution
The solution involves stacking semiconductor die with protection circuits in a small package, where each die is connected in parallel to increase ESD protection capability without increasing the package footprint, using conductive layers, TSVs, and bumps for interconnects, and encapsulating with a non-conductive material for environmental protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the semiconductor package size is increased to include more die area for ESD protection, then the ESD protection capability is improved, but the package footprint increases which contradicts the goal of miniaturization
Solution Approach 1:
The patent transitions from a two-dimensional layout (spreading protection circuits across a larger package area) to a three-dimensional stacked configuration (stacking multiple thin die vertically). This dimensional change allows the system to increase the total silicon surface area for ESD protection while maintaining a small package footprint, as the additional protection capacity is achieved through vertical stacking rather than horizontal expansion.
Solution Approach 2:
The patent implements nesting by stacking multiple protection circuit die vertically, where each die is placed on top of the previous one within the same package footprint. This nested arrangement allows multiple independent protection circuits to be integrated in a compact space, increasing the overall ESD protection capability without expanding the package area.
2Power
If more die area is used to handle higher electric current for ESD protection, then the current handling capability is improved, but the device size increases
Solution Approach 1:
The patent addresses the power-handling contradiction by moving from a planar expansion approach to a vertical stacking approach. Multiple thin die are stacked vertically to increase the total silicon surface area available for current dissipation, thereby enhancing power handling capability while keeping the device footprint and overall volume minimal.
Solution Approach 2:
The patent segments the ESD protection function across multiple separate die, each containing protection circuits. These segmented die are stacked vertically and electrically connected in parallel, allowing the current handling capability to be distributed across multiple smaller units rather than requiring a single large die, thus increasing total power handling while maintaining compact device dimensions.
3Reliability
If multiple protection circuits are integrated in parallel to increase ESD protection, then the protection capability is improved, but the package size increases
Solution Approach 1:
The patent resolves this contradiction by stacking multiple protection circuit die vertically in a three-dimensional configuration. This allows multiple protection circuits to be integrated in parallel with their input terminals electrically connected together, increasing ESD protection capability while maintaining a small package footprint, as the vertical stacking eliminates the need for horizontal expansion.
Solution Approach 2:
The patent merges multiple protection circuit die into a single integrated package through vertical stacking and electrical interconnection. The input terminals of the stacked die are electrically connected in parallel, combining the protection capabilities of multiple circuits into one compact device, thereby achieving enhanced ESD protection without increasing the package footprint.
Data Source
AI summary
A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.