Stacked Die Assembly with Multiple Interposers for Bandwidth Scaling
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Solution Overview
Problem
Integrated circuits (ICs) using Stacked-Silicon Interconnect Technology (SSIT) face bandwidth restrictions due to pin constraints, limiting their ability to support higher communication bandwidths despite having multiple semiconductor dies in a single package.
Innovation Solution
The solution involves a stacked die assembly with interposers that utilize fine pitch interconnects to route signals outside the interconnect restricted areas, allowing for increased pin sites and bandwidth by forming interposers on a single wafer without severing them, and using a bridging die to connect interposers, thereby enhancing interconnect density and reducing stress on individual components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor dies are placed in a single package using SSIT, then the communication bandwidth demand can be addressed, but pin constraints still limit the actual bandwidth
Solution Approach 1:
The patent transitions from two-dimensional pin-based interconnection to three-dimensional stacked die architecture with vertical interconnects. Multiple dies are stacked vertically with interposers providing fine-pitch interconnects between dies, enabling bandwidth scaling beyond pin constraints by utilizing the vertical dimension for signal routing.
Solution Approach 2:
Interposers are introduced as intermediary components between semiconductor dies. These interposers provide fine-pitch interconnect structures that route signals between dies with higher density than traditional pin connections, acting as a mediator that overcomes the bandwidth limitations imposed by direct pin constraints.
2Manufacturing precision
If a single large interposer is used to connect multiple dies, then interconnect density increases, but stress on the interposer and IC structure increases
Solution Approach 1:
The patent divides a single large interposer into multiple smaller interposers, each connecting to a subset of dies. This segmentation reduces the stress and mechanical load on each individual interposer while maintaining high interconnect density through the distributed architecture. The smaller interposers are easier to manufacture and less prone to failure.
Data Source
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AI summary
A stacked die assembly for an IC includes a first interposer (500A); a second interposer (500B); a first integrated circuit die (300, 1110), a second integrated circuit die (303), and a plurality of components (713). The first integrated circuit die (300, 1110) is interconnected to the first interposer (500A) and the second interposer (500B), and the second integrated circuit die (303) is interconnected to the second interposer (500B). The plurality of components (713) interconnect the first integrated circuit die (300, 1110) to the first interposer (500A) and the second interposer (500B). Signals are routed between the first interposer and the second interposer via the first integrated circuit die and the plurality of components. In some exemplary assemblies, the plurality of components that interconnect the first integrated circuit die to the first interposer and the second interposer are located outside an interconnect restricted area (710) of the first interposer and the second interposer, and signals are routed between the first interposer and the second interposer via the first integrated circuit die and the plurality of components, avoiding the interconnect restricted area of the first interposer and the second interposer. Methods of forming these assemblies are also described.