Stacked Semiconductor Die Layout for Compact Through Electrodes
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Solution Overview
Problem
The through electrodes in stacked memory devices occupy a relatively large region, affecting the structural compactness of the devices.
Innovation Solution
A semiconductor structure with a stacked configuration, where each semiconductor die includes a first base, channels, at least one first auxiliary through electrode, and a plurality of connection through electrodes. The first auxiliary through electrode is surrounded by the connection through electrodes, allowing for heat dissipation and a more compact arrangement of through electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through electrodes are used to electrically connect semiconductor dies in stacked memory devices, then electrical connectivity and high performance are achieved, but the area occupied by through electrodes increases, affecting structural compactness
Solution Approach 1:
The patent implements nesting by placing auxiliary through electrodes inside the region occupied by connection through electrodes. Specifically, the auxiliary through electrodes are positioned within the bounding box of the connection through electrodes, allowing one set of electrodes to be nested within the spatial footprint of another, thereby reducing the total area required for through electrode structures while maintaining electrical connectivity functionality
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement of through electrodes to a three-dimensional nested configuration. By utilizing vertical stacking and radial arrangement of auxiliary electrodes within the connection electrode region, the design exploits the third dimension to reduce the projected area footprint while maintaining all necessary electrical connections between stacked semiconductor dies
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement ensures effective heat dissipation and reduces the area occupied by through electrodes, thereby minimizing the size of the semiconductor structure while maintaining high performance and integration.
Implementation Method 1
the first auxiliary through electrode is surrounded by the plurality of connection through electrodes... This arrangement ensures effective heat dissipation
Data Source
AI summary
The present disclosure provides a semiconductor structure, including a stacked structure, wherein the stacked structure includes a plurality of stacked semiconductor dies, and each of the semiconductor dies includes: a first base; a channel provided on the first base; and at least one first auxiliary through electrode and a plurality of connection through electrodes running through the first base, wherein the at least one first auxiliary through electrode is surrounded by the plurality of connection through electrodes, wherein connection through electrodes of adjacent ones of the semiconductor dies are connected through a first electrical connection structure to form a plurality of mutually isolated transmission paths, and each of the transmission paths is connected to at least one channel through at least one connection through electrode thereon.