Stacked Semiconductor Dies with Partial Overlap and Lifting Support

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Solution Overview

Problem

Current semiconductor package technologies face challenges in achieving high integration density and compact size while maintaining electrical connectivity and structural integrity, particularly in stacked semiconductor die configurations.

Innovation Solution

The proposed stack package design includes a configuration of multiple semiconductor dies stacked with adhesive layers and lifting supporters, where each die is vertically and partially overlapping with adjacent dies, and bonding wires connect the dies to the package substrate, allowing for efficient electrical connection and reduced package width and thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple semiconductor dies are stacked vertically to increase integration density, then the package capacity increases, but the package width and thickness increase

Engineering Contradiction:
Improveintegration densityVSAvoidpackage width and thickness
Core Design Contradiction:
Quantity of substanceVSVolume of moving object

Solution Approach 1:

The patent implements a nested stacking configuration where a first stack structure containing first and second semiconductor dies is partially overlapped by a second stack structure containing third and fourth semiconductor dies. The third semiconductor die is disposed on a lifting supporter and vertically overlaps with the second semiconductor die, creating a nested arrangement that reduces the overall package footprint while maintaining high integration density.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent transitions from a single-column vertical stacking approach to a multi-dimensional stacked configuration by introducing lateral offset and partial overlap between stack structures. This dimensional reorganization allows multiple dies to be arranged in three-dimensional space more efficiently, reducing both package width and thickness while increasing the number of stacked dies.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Volume of moving object

If semiconductor dies are closely stacked to reduce package size, then package compactness improves, but electrical connectivity and structural integrity become difficult to maintain

Engineering Contradiction:
Improvepackage sizeVSAvoidelectrical connectivity and structural integrity
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent introduces lifting supporters as intermediary structures between the third semiconductor die and the package substrate. These lifting supporters provide mechanical support and spacing, ensuring structural integrity while allowing close stacking. Additionally, adhesive layers serve as intermediaries between stacked dies, maintaining both mechanical bonding and electrical connectivity through the bonding pads and bonding wires.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies different functional properties to different regions of the package. The lifting supporter is positioned at specific locations to provide localized support where needed, while adhesive layers are applied selectively between dies. The bonding pads and bonding wires are strategically positioned to ensure electrical connectivity is maintained in critical areas while allowing compact stacking elsewhere.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10903189B2Stack packages including stacked semiconductor dies
Publication Date: 2021.01.26 SK HYNIX INC
  • US10903189B2 patent drawing
  • US10903189B2 patent drawing
  • US10903189B2 patent drawing

AI summary

A stack package includes a second semiconductor die stacked on the first semiconductor die, a third semiconductor die disposed on the lifting supporter. The third semiconductor die vertically and partially overlapping with the second semiconductor die.