Stacked Dies on Redistribution Layers for Low-Profile Packages
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Solution Overview
Problem
Conventional integrated packages face challenges in achieving a low profile with high density connections due to the limitations of organic laminate or silicon substrates and the spacing constraints of solder balls as coupling methods, making it difficult to manufacture compact packages with multiple dies.
Innovation Solution
The integration of stacked dies on redistribution layers using dielectric layers with metal pillars and under bump metallization (UBM) layers, along with through substrate vias (TSVs), allows for more efficient electrical coupling and reduced package height, enabling higher density connections and a more compact form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If solder balls are used as coupling method between die and substrate, then electrical connection is achieved, but connection density is limited due to minimum spacing requirements
Solution Approach 1:
The patent transitions from planar solder ball connections to three-dimensional stacked die architecture with through-substrate vias, enabling vertical electrical pathways that increase connection density without increasing lateral spacing requirements
Solution Approach 2:
The substrate is used as an intermediary carrier that hosts multiple dies in a stacked configuration, with through-substrate vias providing direct vertical electrical pathways between dies and the substrate, eliminating the need for extensive solder ball arrays
2Reliability
If organic laminate or silicon substrate is used, then die coupling is achieved, but package profile height increases and manufacturing flexibility is reduced
Solution Approach 1:
The patent changes the substrate thickness parameter and adopts a stacked die configuration to reduce the overall package profile height while maintaining reliable die coupling through through-substrate vias and optimized interconnection structures
3Area of stationary object
If multiple dies are stacked to reduce real estate, then area utilization improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the package into modular stacked dies that can be independently fabricated and then assembled, with through-substrate vias providing standardized interconnection points that simplify the integration process despite the three-dimensional configuration
Data Source
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AI summary
Some features pertain to an integrated device that includes a dielectric layer configured as a base for the integrated device, several redistribution metal layers in the dielectric layer, a first wafer level die coupled to a first surface of the dielectric layer, and a second wafer level die coupled to the first wafer level die. The dielectric layer includes several dielectric layers. In some implementations, the first wafer level die is coupled to the redistribution metal layers through a first set of interconnects. In some implementations, the first wafer level die includes several through substrate vias (TSVs). In some implementations, the second wafer level die is coupled to the redistribution metal layers through a first set of interconnects, the TSVs, a second set of interconnects, and a set of solder balls. In some implementations, the integrated device includes an encapsulation layer that encapsulates the first and second wafer level dies.