Stacked Diode-MOS Capacitor Layout for Higher Capacitance Density
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Solution Overview
Problem
As integrated circuits (ICs) are scaled in size, there is a need for capacitor structures that consume less chip area while exhibiting larger capacitance values to fulfill various functions such as bypass capacitors in filters and compensation capacitors in operational amplifiers.
Innovation Solution
A high-density stacked capacitor structure is developed, comprising a diode-type capacitor in a semiconductor substrate and a transistor-type capacitor on an insulator layer aligned above and connected in parallel, with varying in-substrate well configurations to enhance capacitance density, optionally including additional metal-oxide-metal capacitors in back-end-of-line metal levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional capacitor structures are used, then chip area consumption is acceptable, but capacitance density is insufficient
Solution Approach 1:
The patent transitions from planar capacitor layouts to a three-dimensional stacked configuration, placing a first capacitor and a second capacitor vertically one above the other. This vertical stacking approach utilizes the third dimension (height) to increase capacitance density without proportionally increasing chip area, effectively resolving the contradiction between achieving higher capacitance and minimizing area consumption.
Solution Approach 2:
The patent combines multiple capacitor structures (first capacitor and second capacitor) into a single integrated stacked unit that functions as one high-density capacitor component. By merging these capacitors and connecting them in parallel, the invention achieves higher total capacitance while occupying a compact footprint, thereby improving capacitance density relative to chip area.
2Quantity of substance
If capacitor size is increased to achieve larger capacitance values, then capacitance density improves, but chip area consumption increases
Solution Approach 1:
Instead of increasing capacitor area in the planar direction, the patent stacks capacitors vertically to accumulate capacitance in the vertical dimension. The first capacitor is positioned at a first level and the second capacitor at a second level above it, allowing the system to achieve larger total capacitance values without expanding the horizontal chip footprint.
Solution Approach 2:
The patent implements a nested arrangement where the second capacitor is positioned above and partially aligned with the first capacitor, creating a vertically nested structure. This nesting approach allows multiple capacitor elements to occupy overlapping horizontal projections while being separated vertically, thereby achieving higher capacitance values within a compact area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure achieves higher capacitance density with reduced chip area, effectively serving as bypass capacitors in filters and compensation capacitors in operational amplifiers, thereby optimizing IC performance.
Implementation Method 1
a diode-type capacitor in a semiconductor substrate, an insulator layer on the semiconductor substrate and a transistor-type capacitor on the insulator layer aligned above and connected in parallel with the diode-type capacitor
Data Source
AI summary
Disclosed are a semiconductor structure and method of forming the semiconductor structure. The semiconductor structure includes a high-density stacked capacitor and, particularly, a stack of capacitors connected in parallel between two nodes. The stack includes a diode-type capacitor (also referred to herein as a PN junction capacitor) within a semiconductor substrate. In different embodiments, the diode-type capacitor has different in-substrate well configurations. The stack also includes a transistor-type capacitor (e.g., a metal oxide semiconductor capacitor (MOSCAP)) on an insulator layer aligned above the diode-type capacitor. Optionally, the stack also includes at least one additional capacitor (e.g., at metal-oxide-metal capacitor (MOMCAP)) on a dielectric layer aligned above the transistor-type capacitor (e.g., in one or more back end of the line (BEOL) metal levels).