Stacked Display Transistor Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
As display devices achieve higher resolutions, the decreased distances between transistors, capacitors, and circuit lines lead to increased parasitic capacitance, resulting in display quality degradation, such as spots in horizontal stripes, especially at low brightness and gradient settings.
Innovation Solution
A display device design that includes a specific semiconductor and conductive layer configuration to reduce parasitic capacitance between transistors and circuit lines, ensuring high-quality image display. This involves a first semiconductor layer with defined channel and source-drain areas, and conductive layers with overlapping electrodes and signal lines, carefully arranged to minimize capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of display devices is increased, then the image quality is improved, but the parasitic capacitance between transistors and circuit lines increases, degrading display quality
Solution Approach 1:
The transistor is divided into two separate channel areas (first channel area and second channel area) with corresponding source-drain areas, instead of using a single continuous channel. This segmentation reduces the overlap between the transistor components and circuit lines, thereby reducing parasitic capacitance while maintaining the required resolution
Solution Approach 2:
The patent introduces a vertical stacking dimension by placing conductive layers (first conductive layer, second conductive layer, third conductive layer, fourth conductive layer) at different heights above the substrate. This three-dimensional arrangement allows circuit lines to be positioned above the transistor structures, reducing lateral overlap and parasitic capacitance between transistors and circuit lines
2Area of stationary object
If the distance between transistors, capacitors, and circuit lines is decreased, then the device area is reduced, but the parasitic capacitance increases, causing display defects
Solution Approach 1:
By utilizing vertical stacking with multiple conductive layers positioned at different heights, the patent achieves compact lateral spacing while maintaining electrical isolation. The circuit lines in upper layers can be positioned close to transistors in lower layers without increasing parasitic capacitance, as the vertical separation reduces electromagnetic coupling
Solution Approach 2:
The patent applies different structural configurations to different regions: the first transistor has a specific segmented channel structure, while the second transistor has a different channel area arrangement. This localized optimization allows each transistor region to be designed for minimal parasitic capacitance with adjacent circuit lines
Data Source
AI summary
A display device includes a first semiconductor layer including first and second channel areas, a source-drain area between the first and second channel areas, and a source/drain area extending from the second channel area, a first conductive layer on the first semiconductor layer and including first and second electrodes overlapping the first and second channel areas, respectively, a second semiconductor layer on the first conductive layer and including a third channel area, a second conductive layer on the second semiconductor layer and including a third electrode overlapping the third channel area and a first signal line electrically connected to the second electrode, a third conductive layer on the second conductive layer and including a first conductive region electrically connected to the source/drain area, and a fourth conductive layer on the third conductive layer and including a voltage line electrically connected to the first conductive region.