Stacked DRAM Cell Layout With Dual-Gate Read Transistor
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Solution Overview
Problem
The existing 1T1C DRAM cells face challenges in miniaturization due to increased leakage of stored charge and difficulty in manufacturing capacitors with high integration density, while 2T0C DRAM cells using IGZO transistors offer improved data retention but face disadvantages in stacking height and connection complexity.
Innovation Solution
A stacked DRAM cell structure with two transistors connected to three signal lines, utilizing a dual-gate read transistor and a write transistor, is manufactured using a side recess process, allowing for multi-layer stacking and efficient sharing of source line contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 1T1C DRAM cell is miniaturized to improve integration density, then integration density is improved, but leakage level of stored charge increases and manufacturing difficulty increases
Solution Approach 1:
The read transistor is divided into a dual-gate structure with a main gate and a cut-off gate. The cut-off gate is specifically designed to block sneak currents in unselected cells during read operations, while the main gate controls the selected cell. This segmentation of the gate function resolves the contradiction by maintaining low leakage through the cut-off gate mechanism while preserving the compact 1T1C cell structure for high integration density.
2Duration of action of stationary object
If conventional 2T0C DRAM cell array is used, then data retention is improved, but height of DRAM cell array increases
Solution Approach 1:
The patent transitions from a planar 2T0C structure to a vertical stacked 1T1C structure. By stacking the transistor and capacitor in the vertical dimension rather than arranging them laterally, the cell height is reduced while maintaining the data retention benefits of the 2T0C approach through the dual-gate transistor design that enables reliable charge storage.
3Duration of action of stationary object
If conventional 2T0C DRAM cell structure is used, then data retention is improved, but number of signal lines increases
Solution Approach 1:
The patent merges the word line and source line functions into a single signal line by utilizing the dual-gate transistor configuration. The cut-off gate blocks sneak currents during read operations, enabling the shared line to serve both as a word line for cell selection and as a source line for read operations, thereby reducing the total number of signal lines required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure reduces the area occupied by the DRAM cell array, enables easy multi-layer manufacturing, and improves data retention by leveraging IGZO's low leakage current, while simplifying the layout and manufacturing process.
Implementation Method 1
A main gate of the dual gate is insulated from a storage node by an oxide layer formed on an upper portion of the main gate
Implementation Method 2
The bandgap voltage of IGZO (3.2 eV) is approximately three times larger than that of Si (1.12 eV), and IGZO exhibits a very large asymmetric mobility between electrons and holes. As a result, the leakage current of IGZO is much lower than the leakage current of Si.
Data Source
AI summary
Provided is a stacked DRAM cell having a structure that includes two transistors, capable of being electrically connected to three signal lines, and effective for multi-layer stacking using a side recess process. The stacked DRAM cell has a write transistor and a dual-gate read transistor that includes a cut-off gate and a main gate, and has a structure in which a layer where a source line is formed, a layer where a cut-off gate channel is formed, a layer where a cut-off gate oxide layer is formed, a layer where a main gate channel is formed, a layer where a main gate oxide layer is formed, a layer where a storage node is formed, a layer where a write transistor channel is formed, a layer where a write transistor oxide layer is formed, and a layer where a write word line is formed are sequentially stacked.