Stacked FeRAM Capacitor Arrays With Shared Plates and Single-Transistor Access
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Solution Overview
Problem
Current ferroelectric random-access memory (FeRAM) devices face challenges in achieving higher density and lower volatility, which limits their potential for improving system performance and reducing costs in complex systems.
Innovation Solution
The solution involves increasing the density of FeRAM devices by using multiple bits per access transistor, sharing capacitor plates among capacitors, and employing small access transistors with narrow channels within nanowires or nanosheets, along with ferroelectric materials like lead zirconium titanate (PZT) to enhance memory density and reduce leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional FeRAM structures are used, then device simplicity is maintained, but memory density and volatility performance are insufficient
Solution Approach 1:
The patent transitions from planar transistor structures to vertically stacked three-dimensional transistor configurations. Multiple access transistors are stacked along the vertical dimension, enabling higher memory density while maintaining access control functionality. This dimensional change allows more memory cells to be packed into the same footprint area.
Solution Approach 2:
The patent implements nested structures where capacitors are positioned within or around the stacked transistor structures. The capacitor plates are arranged concentrically or in nested configurations, with inner and outer plates surrounding the nanowire channels. This nesting enables efficient use of three-dimensional space while maintaining electrical isolation and functionality.
2Reliability
If capacitor plates are shared among multiple capacitors, then memory density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the capacitor structure into segmented plates - inner plates and outer plates - that can be independently formed and positioned. Each capacitor is defined by specific combinations of these segmented plates, allowing for modular manufacturing. The segmentation enables shared plates to be precisely aligned with multiple capacitors through standardized interface geometries.
Solution Approach 2:
The patent designs universal capacitor plate structures that serve multiple functions: they act as electrodes for capacitance storage, as shared common plates for multiple capacitors, and as structural elements for mechanical support and alignment. This multi-functionality reduces the total number of discrete components needed while maintaining manufacturing feasibility through standardized fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of denser, more stable, and less volatile FeRAM devices, allowing for smaller component sizes, reduced system temperatures, and increased memory capacity, thereby improving system performance and reducing costs.
Implementation Method 1
a ferroelectric material between the shared inner plate and the outer plate
Implementation Method 2
a nanowire or nanosheet comprising a channel region and a common capacitor plate region
Data Source
AI summary
Bits are stored in an array with multiple capacitors per access transistor. An array of multiple ferroelectric capacitors shares a nanowire or nanosheet as a common plate and stores information accessed by a single common select transistor, which uses the nanowire or nanosheet for its channel. In an integrated circuit (IC) system, a group of bitlines is connected to a capacitor array by arrays of nanowires or nanosheets and wordline-controlled non-planar transistors. An IC die with a capacitor array accessed by a single select transistor and sharing a nanowire or nanosheet is coupled to a power supply and a cooling structure.