Stacked Ferroelectric C-Element Circuits for Low-Voltage Async Logic
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Solution Overview
Problem
Existing asynchronous logic circuits face challenges in operating efficiently at low voltage conditions due to the need for stacks of transistors between the power supply rail and ground rail, leading to increased power consumption and reduced area efficiency.
Innovation Solution
The development of asynchronous circuits using threshold gates and majority/minority gates with capacitive input circuits, which reduce the stack of devices between the supply node and ground, allowing operation at lower power supply levels and providing area reduction and higher throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If stacks of transistors are used between power supply rail and ground rail in asynchronous logic circuits, then logic functionality is achieved, but area consumption increases and power consumption increases
Solution Approach 1:
The patent transitions from planar transistor stacking to three-dimensional vertically stacked capacitor structures. By utilizing the vertical dimension with multiple capacitor layers stacked along the third dimension, the circuit achieves enhanced functionality without proportionally increasing the planar footprint, thereby reducing area consumption while maintaining logic functionality.
Solution Approach 2:
The vertically stacked capacitor structure serves multiple functions simultaneously: it provides capacitive coupling for signal transmission, enables logic threshold control through adjustable capacitance ratios, and implements both majority and minority gate functions. This multi-functionality eliminates the need for separate transistor stacks, reducing overall circuit area.
2Ease of manufacture
If stacks of transistors are used between power supply rail and ground rail in asynchronous logic circuits, then logic functionality is achieved, but power consumption increases
Solution Approach 1:
The patent replaces the traditional transistor-based switching mechanism with a capacitor-based threshold gate mechanism. The vertically stacked capacitors control signal transmission through electrostatic coupling and threshold voltage effects rather than through transistor channel conduction, reducing dynamic power consumption associated with transistor switching and leakage currents.
Solution Approach 2:
The invention changes the operating parameters by using capacitive voltage division and threshold effects instead of transistor gate control. The adjustable capacitance ratios in the vertical stack allow optimization of threshold voltages to minimize power consumption while maintaining adequate noise margins and logic level differentiation.
3Ease of manufacture
If traditional asynchronous logic circuits are used, then circuit functionality is achieved, but throughput is limited
Solution Approach 1:
The patent segments the signal transmission path into multiple parallel capacitive coupling stages within the vertical stack. This segmentation allows independent optimization of each stage's capacitance values to maximize signal propagation speed and enables pipelining of logic operations, thereby increasing overall circuit throughput.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The new asynchronous circuits achieve a 3× reduction in area and 2× higher throughput compared to traditional circuits, enabling efficient operation at less than 1V, while also allowing for flexible logic function implementation by adjusting the switching threshold of capacitive input circuits.
Implementation Method 1
the first and second capacitors are ferroelectric capacitors
Implementation Method 2
a first capacitor coupled to a first input and a second capacitor coupled to a second input, wherein second terminal of the first capacitor and a second terminal of the second capacitor are connected to a summing node
Data Source
AI summary
Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.