Stacked FET Contact Geometry for Shorting and Capacitance Control

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Solution Overview

Problem

Current stacked field-effect transistor (FET) architectures face issues such as shorting and parasitic capacitance due to the design of the bottom contact and top epitaxy, leading to reduced device density and performance.

Innovation Solution

The top active region is patterned with a sloped shape similar to the inner surface of the bottom contact, and a dielectric filled trench with a self-aligning process is used to form consistent spacing between the bottom contact and top epitaxy, ensuring minimal gap and reducing the need for additional space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the bottom contact is offset to prevent shorting with the top active region, then shorting is prevented, but the area increases and CFET density decreases

Engineering Contradiction:

Improveshorting preventionVSAvoiddevice area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The top active region is designed with an asymmetric tapered shape where the width at the top surface is smaller than the width at the bottom surface. This asymmetric geometry allows the bottom contact to be positioned closer to the top active region without causing shorting, as the narrowing top portion provides natural spacing while maintaining electrical isolation.

Inventive Principle:

Principle #4Asymmetry

Solution Approach 2:

The invention changes the geometric parameters of the top active region by creating a tapered structure with different widths at the top and bottom surfaces. This parameter change enables optimized positioning of the bottom contact, reducing the offset distance while preventing shorting through the narrowed top geometry.

Inventive Principle:

Principle #35Parameter changes

2Manufacturing precision

If the bottom contact is offset to maintain consistent spacing, then spacing consistency is improved, but parasitic capacitance increases

Engineering Contradiction:

Improvespacing consistencyVSAvoidparasitic capacitance

Core Design Contradiction:

Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The tapered asymmetric shape of the top active region enables the bottom contact to maintain consistent spacing distance while minimizing the overall area occupied. The narrowing top width reduces the parasitic capacitance between the bottom contact and top active region while the consistent spacing is maintained through the structured geometry.

Inventive Principle:

Principle #4Asymmetry

3Reliability

If additional space is provided for bottom contact positioning, then shorting is prevented, but CFET density decreases

Engineering Contradiction:

Improveshorting preventionVSAvoidCFET density

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The asymmetric tapered top active region with smaller top width than bottom width allows bottom contacts to be positioned closer together without increasing overall device area. This maintains high CFET density while the tapered geometry provides sufficient spacing to prevent shorting between adjacent structures.

Inventive Principle:

Principle #4Asymmetry

Data Source

PatentUS12615812B2Stacked field-effect transistors

Publication Date: 2026.04.28 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

Provided is a stacked field-effect transistor (FET). The stacked FET comprises a top active region. The width of the top of the top active region is smaller than the width of bottom of the top active region. The stacked FET further comprises a top contact in direct contact with a top surface of the top active region. The stacked FET further comprises a bottom active region located substantially below the top active region. The stacked FET further comprises a bottom contact in direct contact with a top surface of the bottom active region. The bottom contact is wider at a top end than at a bottom end.