Stacked FET Power Layout Using Interdevice Power Delivery
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling stacked transistor devices due to spatial and electrical constraints, particularly in cell height scaling, as pitch approaches physical limits, complicating chip layout and performance requirements.
Innovation Solution
The implementation of interdevice power delivery through power lines positioned between vertically stacked field effect transistors (FETs), allowing for reduced cell height and improved integration density by relocating power lines to a central interdevice region, which can be vertically aligned or misaligned, and utilizing dielectric material to separate gate conductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If power lines are positioned at the periphery of stacked transistor devices, then electrical connections can be established, but cell height cannot be scaled down and layout area is increased
Solution Approach 1:
The patent moves power lines from the peripheral plane to the central interdevice region between stacked transistor levels, utilizing the vertical dimension and interdevice space. This repositioning allows power delivery without increasing layout area while enabling cell height scaling by freeing up peripheral space for signal lines.
Solution Approach 2:
The power lines are nested within the interdevice region between the first and second transistor levels, utilizing the existing vertical structure. This nesting approach allows power delivery infrastructure to be integrated within the device stack rather than occupying additional lateral space.
2Quantity of substance
If pitch is reduced to increase integration density, then more devices can be packed on chip, but spatial and electrical constraints make layout more complicated
Solution Approach 1:
By moving power lines to the interdevice region and utilizing vertical stacking, the patent reduces the lateral pitch requirements for power distribution. This enables higher integration density while simplifying layout by separating power delivery from signal routing in different spatial dimensions.
3Length of stationary object
If power lines are relocated to the interdevice region, then cell height scaling is enabled and layout area is reduced, but fabrication complexity may increase
Solution Approach 1:
The interdevice region is utilized for multiple purposes: it provides structural separation between transistor levels, serves as the location for power line placement, and enables dielectric material positioning for gate conductor separation. This multi-functionality reduces overall device complexity despite the relocated power lines.
4Quantity of substance
If vertically stacked transistors are positioned close together to increase areal density, then integration density improves, but spatial constraints make it challenging to provide required performance
Solution Approach 1:
The device is segmented into distinct vertical levels with an interdevice region separating them. This segmentation allows close vertical stacking for high areal density while maintaining electrical isolation and performance through the interdevice region, which houses power lines and dielectric materials separately from the active transistor regions.
Data Source
AI summary
A semiconductor device includes a stacked transistor structure having field effect transistors on two vertically stacked levels. An interdevice region is disposed between the two vertically stacked levels. A first power line is disposed within the interdevice region, and a second power line is disposed within the interdevice region and vertically spaced from the first power line.