Interlevel Via Layout for Stacked FET Backside Power Routing
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Solution Overview
Problem
The challenge in semiconductor device fabrication lies in forming reliable connections between stacked FETs, particularly in separating power delivery components from signal wires, where the top device can shadow the bottom device during contact formation, making it difficult to connect source/drain regions to signal lines or power supplies effectively.
Innovation Solution
The implementation of a backside power delivery network (BSPDN) and middle-of-line (MOL) contacts, along with interlevel vias, allows for the electrical connection of top source/drain regions to the BSPDN, while maintaining separate connections to BEOL metal levels, thereby improving routability and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If stacked FETs are used to increase transistor density, then the number of transistors per chip area increases, but the top device shadows the bottom device during contact formation, making it difficult to establish reliable electrical connections
Solution Approach 1:
The patent introduces a vertical dimension for power delivery by implementing a backside power delivery network (BSPDN) that routes power connections from the rear of the substrate. This separates the vertical space used by signal wires on the frontside from power delivery, allowing the top FET to be connected to the BSPDN through the substrate without interfering with bottom FET signal connections, thus resolving the shadowing problem while maintaining high transistor density
Solution Approach 2:
The patent segments the interconnect functions by separating power delivery from signal routing. Power connections are routed through the backside via the BSPDN, while signal wires remain on the frontside. This segmentation allows independent optimization of power and signal paths, enabling reliable connections for both top and bottom FETs without mutual interference
2Device complexity
If power delivery components and signal wires are integrated on the same layer, then routing complexity is reduced, but parasitic capacitance increases and routability decreases
Solution Approach 1:
The patent utilizes the substrate thickness dimension to separate power and signal paths. The BSPDN is formed on the backside of the substrate at a different vertical level from the frontside signal wires, creating physical separation that reduces parasitic capacitance while maintaining routing efficiency through the vertical power delivery path
Data Source
AI summary
Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first top transistor comprising a first source/drain (S/D) region and a first bottom transistor with a second S/D region. The first bottom transistor may be stacked directly below the first transistor. The semiconductor structure may also include a backside power delivery network (BSPDN) below the bottom transistor, a back-end-of-line (BEOL) metal level above the top transistor, and a first interlevel via electrically connecting a top of the first S/D region to the BSPDN.