Stacked FET RF Switch Bias Network for Better Linearity
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Solution Overview
Problem
Transistor-based RF switches face stringent linearity requirements due to downlink and uplink carrier aggregation, necessitating improved linearity performance to maintain low noise levels below −115 dBm in complex RF systems.
Innovation Solution
A transistor-based RF switch design featuring N main FETs stacked in series with a gate bias network including gate resistors and capacitors to balance gate and body bias voltages, reducing harmonic distortion by over 30 dB compared to previous designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional RF switch designs are used, then device complexity is reduced, but linearity performance deteriorates and harmonic distortion increases
Solution Approach 1:
The gate bias network is segmented into multiple independent resistors, with each resistor connected to the gate terminal of a specific FET. This segmentation allows individual control and optimization of bias voltages for each transistor, improving overall linearity performance while managing device complexity through modular design
Solution Approach 2:
Different bias voltages are applied locally to each FET's gate terminal through the segmented resistor network. This local quality approach enables precise control of each transistor's operating point, reducing harmonic distortion and improving linearity performance by optimizing each component's contribution to the overall system
2Manufacturing precision
If the number of main FETs is increased to improve linearity, then harmonic distortion is reduced, but insertion loss increases
Solution Approach 1:
The bias voltage parameters are optimized and balanced across all FETs in the series stack. By carefully controlling the gate and body bias voltages, the system achieves improved linearity and reduced harmonic distortion while minimizing the cumulative insertion loss that would normally increase with more series FETs
3Adaptability or versatility
If carrier aggregation is implemented to increase communication capacity, then system complexity increases, but linearity requirements become more stringent
Solution Approach 1:
The balanced bias voltage network provides feedback control mechanisms that automatically adjust and maintain optimal bias conditions across all FETs. This feedback approach ensures consistent linearity performance regardless of the communication mode or carrier aggregation configuration, meeting stringent linearity requirements while supporting high communication capacity
Data Source
AI summary
Disclosed is a transistor-based switch having an N number of main field-effect transistors (FETs) stacked in series such that a first terminal of a first main FET of the N number of main FETs is coupled to a first end node and a second terminal of an Nth main FET of the N number of main FETs is coupled to a second end node, wherein N is a finite number greater than five. The transistor-based switch further includes a gate bias network having a plurality of gate resistors, wherein individual ones of the plurality of gate resistors are coupled to gate terminals of the N number of main FETs. A common gate resistor is coupled between a gate control input and a gate control node of the plurality of gate resistors, and a capacitor is coupled between the gate control node and a switch path node of the main FETs.