Stacked FET SOT-MRAM Layout for Higher Cell Density
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Solution Overview
Problem
Three-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) devices face a density penalty due to requiring two transistors per cell for read and write operations, resulting in increased area usage compared to other configurations like one transistor per resistive RAM (RRAM) magnetic tunnel junctions.
Innovation Solution
A stacked FET configuration is implemented with a first type FET driving an SOT line and a second type FET connected to a magnetic tunnel junction, where the first type FET is disposed above the second type FET, allowing for a density of three contacted poly pitch (CPP) per two cells, achieved through wafer bonding and nanosheet technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If two transistors per cell are used for read and write operations in SOT MRAM, then read and write operations can be performed separately, but the areal density increases and the device becomes impractical
Solution Approach 1:
The patent transitions from a planar two-transistor configuration to a vertical stacked configuration, utilizing the third dimension (vertical stacking) to reduce the footprint area. The stacked FETs are arranged vertically with source/drain regions extending through multiple layers, allowing separable read/write operations while reducing the horizontal cell area to 3 CPP per 2 cells.
2Device complexity
If a wide nanosheet configuration is used to implement SOT MRAM, then the device structure can be simplified, but the configuration becomes impractical for implementation
Solution Approach 1:
The patent divides the nanosheet structure into multiple thin stacked layers rather than using a single wide nanosheet. The stacked FETs are formed with multiple nanosheet layers stacked vertically, each layer contributing to the transistor structure. This segmentation allows for practical manufacturing using standard nanosheet fabrication processes while achieving the required device functionality.
3Area of stationary object
If stacked FET configuration is used, then the areal density is improved, but the fabrication process complexity increases
Solution Approach 1:
The patent employs universal fabrication processes that are already established for nanosheet and FinFET technologies. The stacked FET structure utilizes the same source/drain epitaxy, nanosheet formation, and gate patterning processes used in conventional nanosheet devices. The isolation oxide contacts and wafer bonding techniques are integrated into existing CMOS fabrication flows, reducing the impact of added complexity.
Solution Approach 2:
The patent implements a nested structure where one FET is stacked within the footprint of another FET, with the bottom FET's source/drain regions serving as part of the top FET's structure. The isolation oxide contacts are nested within the stacked configuration, and wafer bonding is used to nest multiple device layers together. This nesting approach maximizes space utilization while following a systematic fabrication sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration doubles the areal density of current SOT MRAM schemes while being compatible with nanosheet, FinFET, and monolithic transistor integration, and allows for enhanced pFET current drive through orientation engineering and high mobility channel materials.
Implementation Method 1
allowing to switch at sub 1 nanosecond (ns) regime using a different write mechanism, such as spin-orbit coupling
Data Source
AI summary
Embodiments are disclosed for a three-terminal spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) device. The three-terminal SOT MRAM device includes a first type field effect transistor (FET) that drives an SOT line. Additionally, the first type FET includes a write gate in electrical contact with a write wordline (WWL). Further, the device also includes a second type FET in electrical contact with a magnetic tunnel junction (MTJ). Also, the second type FET comprises a read gate in electrical contact with a read wordline (RWL). Additionally, the first type FET is disposed above the second type FET. Further, the three-terminal SOT MRAM device provides a density of three contacted poly pitch (CPP) per two cells.