Stacked-Fin Semiconductor Structure Using Air Gaps to Cut Gate Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor structures face challenges with high parasitic capacitance between the source/drain doped layer and the metal gate, which affects the electrical performance due to the high dielectric constant material filling the auxiliary recesses.
Innovation Solution
A semiconductor fabrication method that forms auxiliary recesses between the source/drain doped layer and the metal gate, where an isolation layer is partially filled, creating an air gap with a low dielectric constant, thereby reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k metal gate is introduced to solve leakage and resistance problems, then gate dielectric leakage is reduced and gate electrode resistance is lowered, but parasitic capacitance between source/drain doped layer and metal gate increases
Solution Approach 1:
The patent introduces an intermediary material layer between the source/drain doped layer and the metal gate. This intermediary layer has a lower dielectric constant than the high-k gate dielectric, thereby reducing the parasitic capacitance while maintaining the low leakage and low resistance benefits of the high-k metal gate structure.
Solution Approach 2:
The patent applies different dielectric materials with different properties to different regions: high-k dielectric material is used in the gate dielectric layer for low leakage, while a lower-k dielectric material is used in the intermediary layer between source/drain and gate to reduce parasitic capacitance. This local differentiation of material properties resolves the contradiction between these two opposing requirements.
2Area of moving object
If transistor size is continuously reduced to improve integration density, then device miniaturization is achieved, but gate dielectric leakage increases and gate electrode resistance increases
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate dielectric material by using high-k material instead of traditional silicon oxide. This parameter change allows the gate dielectric layer to maintain effective electrical isolation even when scaled to thinner dimensions, thereby reducing leakage current in miniaturized transistors.
Solution Approach 2:
The patent employs composite material structures including high-k gate dielectric combined with metal gate, and further combines different dielectric materials with different dielectric constants in layered configurations. These composite structures provide both low leakage and low resistance characteristics that enable continued transistor scaling.
3Stability of the object's composition
If isolation layer completely fills auxiliary recesses to provide structural support, then mechanical stability is improved, but parasitic capacitance increases due to high dielectric constant material
Solution Approach 1:
The patent applies local quality by using a lower-k dielectric material specifically in the intermediary layer within the auxiliary recesses, while other regions may use different materials. This localized material selection provides structural support where needed while minimizing parasitic capacitance in critical areas adjacent to the source/drain doped layers.
Solution Approach 2:
The patent changes the dielectric constant parameter of the material filling the auxiliary recesses from high-k to lower-k material. This parameter change reduces the parasitic capacitance formed between the source/drain doped layer and the gate region, while the material still provides sufficient mechanical support and structural stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic capacitance by utilizing an air gap with a dielectric constant similar to vacuum, improving the electrical performance of the semiconductor structure.
Implementation Method 1
utilizing an air gap with a dielectric constant similar to vacuum, thereby reducing parasitic capacitance
Data Source
AI summary
A semiconductor structure and fabrication method are provided. The fabrication method includes providing a substrate and a fin protruding from the substrate, the fin including stacked structures and each stacked structure including a sacrificial layer and a semiconductor layer on the sacrificial layer; forming a dummy gate across the fin; etching the fin on two sides of the dummy gate to form source/drain recesses; etching the sacrificial layer of the fin at the bottom of the dummy gate exposed by the source/drain recesses to form auxiliary recesses along an extension direction of the fin; forming an isolation layer on the bottoms of the auxiliary recesses without completely filling the auxiliary recesses; and forming a source/drain doped layer completely filling the source/drain recesses, the source/drain doped layer and the isolation layer enclosing an air gap.