Stacked Forksheet Transistor Architecture for Sub-3 nm Density Scaling
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Solution Overview
Problem
The challenge in integrated circuit fabrication is to maintain performance and density as transistor dimensions scale below 10 nanometers, particularly in achieving optimal spacing and interconnection between features in semiconductor stacks, which is hindered by lithographic constraints and the trade-off between critical dimension and spacing.
Innovation Solution
The implementation of stacked forksheet transistors with a self-aligned dielectric wall and nanoribbon or nanowire transistors, allowing for a 3-D CMOS architecture that reduces spacing between transistors and enables higher density and improved interconnect architectures by using a backbone dielectric material and shared-gate configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor dimensions are scaled down to increase density, then the number of devices per chip increases, but the spacing between features becomes insufficient due to lithographic constraints
Solution Approach 1:
The patent transitions from planar 2D transistor layout to three-dimensional stacked architecture, where multiple transistor layers are vertically stacked above each other. This dimensional change allows increased device density without further reducing lateral feature spacing, as devices are arranged in the vertical dimension rather than competing for lateral space.
Solution Approach 2:
The patent implements nested structures where semiconductor channels are surrounded by gate structures, which are in turn surrounded by dielectric materials. Multiple transistor layers are nested vertically, with each layer containing channels, gates, and isolation structures nested within one another, maximizing space utilization.
2Quantity of substance
If critical dimension is reduced to increase density, then device capacity increases, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent employs preliminary patterning actions where mandrel structures and spacer layers are formed first, followed by selective etching to define the final transistor features. This multi-step self-aligned process ensures precise feature dimensions are maintained even as critical dimensions are reduced, as each step builds upon the previous with built-in alignment.
Solution Approach 2:
The patent utilizes selective etching parameters and material composition variations to maintain manufacturing precision. By changing etch selectivity parameters and using differentiated dielectric materials with distinct etch rates, the process maintains precise dimensional control across varying feature sizes.
3Quantity of substance
If transistor size is reduced to increase density, then chip capacity increases, but short channel control becomes more challenging
Solution Approach 1:
The patent implements three-dimensional stacked transistor architecture with vertical channel structures surrounded by gate structures on multiple sides. This 3D configuration provides enhanced gate control over the channel in the vertical dimension, improving short channel control as device dimensions are reduced and multiple devices are stacked to increase capacity.
4Quantity of substance
If feature spacing is reduced to increase density, then device density increases, but lithographic process constraints become more severe
Solution Approach 1:
The patent resolves lithographic constraints by moving device placement from the lateral plane to the vertical dimension. Multiple transistor layers are stacked vertically with spacing between layers defined by thin dielectric films, allowing high device density without requiring further reduction of lateral feature pitch that would exceed lithographic capabilities.
Solution Approach 2:
The patent segments the transistor structure into distinct lateral and vertical components, with lithography defining the lateral footprint and subsequent vertical stacking processes defining the vertical architecture. This segmentation allows lithography to work at relaxed lateral pitch while density is achieved through vertical multiplication of devices.
Data Source
AI summary
Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.