Stacked Multi-Gate GAA Structure for Balanced nFET and pFET Current
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Solution Overview
Problem
Existing semiconductor technologies face challenges in achieving balanced driving currents from stacked gate-all-around (GAA) transistors, particularly as they transition to sub-10 nanometer technology nodes, where n-type and p-type FETs often require different numbers of semiconductor channel layers to achieve balanced performance.
Innovation Solution
The approach involves forming stacked GAA transistors with varying numbers of active channel layers, where at least one stack has floating channel layers, allowing for balanced current driving by adjusting the number of active channel layers in each transistor, and using a common gate structure for both transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same number of semiconductor channel layers are used in both nFET and pFET, then the fabrication process is simplified, but the current driving capability becomes unbalanced
Solution Approach 1:
The patent applies local quality by making the channel layer configuration different for nFET and pFET devices. Specifically, the nFET includes a first number of semiconductor channel layers while the pFET includes a second number of semiconductor channel layers, where these numbers are deliberately different to balance the current driving capability of each transistor type. This local differentiation resolves the contradiction by allowing simplified bulk fabrication processes while achieving device-level performance balance.
2Reliability
If different numbers of semiconductor channel layers are used in nFET and pFET to balance current driving capability, then performance balance is improved, but the fabrication complexity increases
Solution Approach 1:
The patent employs segmentation by dividing the semiconductor structure into distinct regions with different channel layer configurations. The nFET region contains a first number of channel layers while the pFET region contains a second number, allowing independent optimization of each transistor type's performance. This segmentation enables balanced current driving capability without requiring complete redesign of the entire fabrication process.
Solution Approach 2:
The patent applies parameter changes by varying the number of semiconductor channel layers as a key structural parameter to control device performance. By adjusting this parameter differently for nFET and pFET devices, the patent achieves balanced current driving capability. This parameter-based approach allows performance optimization through material and structural variations rather than complex process changes.
3Productivity
If more semiconductor channel layers are added to increase device density, then production efficiency improves, but the processing complexity at sub-10 nanometer nodes increases
Solution Approach 1:
The patent transitions from planar transistor architectures to vertically stacked multi-gate structures, moving the scaling dimension from two-dimensional lateral scaling to three-dimensional vertical stacking. This dimensional change allows continued increase in device density and production efficiency at sub-10 nanometer nodes by exploiting the vertical dimension, thereby avoiding the processing complexity that would result from further lateral scaling.
Data Source
AI summary
A semiconductor device according to the present disclosure includes a stack of first channel layers and first and second source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively. The first and second S/D epitaxial features have a first conductivity type. The semiconductor device also includes a stack of second channel layers stacked over the first channel layers and third and fourth source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the second channel layers, respectively. The third and fourth S/D epitaxial features have a second conductivity type. A total active channel layer number of the first channel layers is different from that of the second channel layers.