Stacked Nanosheet GAA FET Structure for Short-Channel Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving full depletion in the channel region of gate-all-around (GAA) FETs due to the fourth side of the channel being far from the gate electrode, leading to short-channel effects and sub-threshold current swing issues as transistor dimensions are scaled down to sub 10-15 nm technology nodes.
Innovation Solution
The development of a GAA FET with vertically stacked multiple channels in the form of nanosheets or nanowires, surrounded by a gate dielectric layer and gate electrode, incorporating specific materials and structures to enhance control and depletion, including buffer layers, gate dielectric materials, and epitaxial layers to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional Fin FET gate structure is used where the gate electrode is adjacent to three side surfaces of the channel region, then the transistor has three gates controlling the current through the fin, but the bottom part of the channel is far away from the gate electrode and thus is not under close gate control, leading to short-channel effects
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional gate-all-around structure where the gate electrode completely surrounds the channel region including the bottom surface. This dimensional change enables the gate to control the channel from all directions (top, bottom, and sides), achieving fuller depletion and eliminating the short-channel effects that plague conventional Fin FETs where the bottom of the channel was inaccessible to gate control.
2Productivity
If transistor dimensions are scaled down to sub 10-15 nm technology nodes to achieve higher device density and performance, then device density and performance improve, but short-channel effects and leakage currents increase
Solution Approach 1:
The gate-all-around structure provides three-dimensional electrostatic control that becomes increasingly effective as device dimensions scale down. By surrounding the channel completely, the gate maintains strong control over the channel region even at sub-10-15 nm nodes, preventing the short-channel effects and leakage currents that typically worsen with scaling.
Solution Approach 2:
The gate electrode is nested around the channel region in a complete enclosure, with the gate dielectric layer interposed between the gate electrode and channel. This nested configuration ensures that the gate control extends uniformly to all surfaces of the channel including the bottom, providing consistent electrostatic control regardless of the specific transistor dimensions.
3Device complexity
If the gate structure surrounds the fin on three surfaces in a Fin FET, then the transistor essentially has three gates controlling the current through the fin, but the fourth side (bottom part of the channel) is not under close gate control
Solution Approach 1:
The patent adds the fourth dimension of gate control by extending the gate electrode to surround the bottom surface of the channel region. This completes the enclosure from the three-sided gate structure of conventional Fin FETs to a true four-sided gate-all-around structure, achieving complete spatial control over the channel.
Solution Approach 2:
The gate-all-around structure serves multiple functions simultaneously: it provides electrostatic control over all channel surfaces, defines the channel region boundaries, and enables fuller depletion. This universal gate structure replaces the need for separate control mechanisms for different channel surfaces.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure protruding from a substrate, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer is formed on an end of each of the etched first semiconductor layers. One or more epitaxial layers are formed in the source/drain space, and the sacrificial gate structure is replaced with a metal gate structure. A width of the source/drain space at a bottommost one of the first semiconductor layers is greater than a width of the source/drain space at one of the first semiconductor layers above the bottommost one of the first semiconductor layers.