Stacked GAA Gate Spacer Structure for Nanoribbon Isolation
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Solution Overview
Problem
The challenge in forming gate spacer structures in stacked transistor devices is the uneven spacing between nanoribbons, which leads to fabrication challenges such as parasitic capacitance and shorting between gate electrodes and source or drain regions, due to the difference in vertical spacing between upper and lower nanoribbons.
Innovation Solution
The solution involves forming gate spacer structures in sections using separate etching and deposition processes with sacrificial materials that are etch selective, allowing for the creation of vertical and horizontal sections with varying dimensions, ensuring proper spacing and reducing the risk of parasitic capacitance and shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate spacer formation is used in stacked transistor devices, then manufacturing simplicity is maintained, but uneven spacing between nanoribbons causes parasitic capacitance and shorting between gate electrodes and source or drain regions
Solution Approach 1:
The gate spacer structure is divided into multiple sections (first section and second section) with different lateral dimensions. The first section has a first lateral dimension and the second section has a second lateral dimension, where the first dimension differs from the second dimension by at least 1 nm. This segmentation allows each section to be optimized for specific spacing requirements between nanoribbons, resolving the uneven spacing issue while maintaining manageable fabrication through modular construction.
2Reliability
If gate spacer structures are formed with varying dimensions to accommodate uneven nanoribbon spacing, then parasitic capacitance and shorting are reduced, but fabrication precision requirements increase
Solution Approach 1:
Different sections of the gate spacer structure are given different lateral dimensions to match the local spacing requirements between nanoribbons. The first section is sized for one spacing interval while the second section is sized for another spacing interval. This local quality approach ensures that each part of the structure has the precise dimensions needed for its specific location, achieving electrical isolation without requiring ultra-precision fabrication across the entire structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of gate spacer structures with a planar or linear outer sidewall, facilitating the separation of gate structures from source and drain regions, thereby improving the reliability and efficiency of the stacked transistor device architecture.
Implementation Method 1
separate etching and deposition processes with sacrificial materials that are etch selective
Implementation Method 2
separate etching and deposition processes with sacrificial materials
Data Source
AI summary
An integrated circuit includes an upper semiconductor body extending in a first direction from an upper source region to an upper drain region, and a lower semiconductor body extending in the first direction from a lower source region to a lower drain region. The upper body is spaced vertically from the lower body in a second direction orthogonal to the first direction. A gate spacer structure is adjacent to the upper and lower source regions. In an example, the gate spacer structure includes (i) a first section having a first dimension in the first direction, and (ii) a second section having a second dimension in the first direction. In an example, the first dimension is different from the second dimension by at least 1 nm. In some cases, an intermediate portion of the gate spacer structure extends laterally within a given gate structure, or between upper and lower gate structures.