Stacked Gate Electrode Structure for Nonvolatile Memory
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Solution Overview
Problem
Nonvolatile semiconductor memory cells with MONOS structure face challenges in erasing data due to insufficient injection of holes through the tunnel insulating film and short-channel effects caused by reduced gate length, leading to degradation in write/erase characteristics and increased risk of short-circuiting between adjacent gate electrodes.
Innovation Solution
A nonvolatile semiconductor storage device with a gate electrode structure comprising multiple stacked layers, where the first gate electrode layer is in contact with the block insulating film, the second layer is made of polysilicon with edges retracting relative to the first layer, and the third layer is a metal silicide, allowing for increased gate length and reduced fringe capacitance, thereby preventing short-channel effects and improving erase characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate length dimension is increased to prevent short-channel effects, then the reliability of memory cell transistors is improved, but the space between adjacent gate electrodes is reduced, causing short-circuiting
Solution Approach 1:
The gate electrode is divided into multiple layers (first gate electrode layer and second gate electrode layer) with different materials and functions. The first layer provides the primary gate function with sufficient length, while the second layer is positioned only over the active region, preventing short-circuiting between adjacent gates while maintaining reliable transistor operation.
Solution Approach 2:
Different portions of the gate structure have different properties: the first gate electrode layer extends across the entire gate region including inter-gate areas, while the second gate electrode layer is localized only over the active channel region. This local differentiation allows the gate to provide both sufficient length for reliability and spatial separation to prevent short-circuiting.
2Reliability
If a stacked gate structure with oxide films is used to extend gate length, then the short-channel effect is suppressed, but the gate length is reduced due to oxide film thickness and the structure becomes complex requiring anti-oxidation films
Solution Approach 1:
The invention extracts and removes the problematic oxide films and anti-oxidation layers from the gate structure. Instead of using a complex stacked gate with multiple insulating and conductive layers, the patent employs a simplified two-layer metal gate structure where the first metal layer直接接触 the high-k dielectric, eliminating the need for oxide barrier layers and reducing overall gate complexity while maintaining effective gate length.
Solution Approach 2:
The gate electrode uses a composite structure of two different metal materials: the first gate electrode layer uses a metal with high work function (e.g., tungsten, platinum) for optimal interface with the high-k dielectric, while the second gate electrode layer uses a different metal (e.g., aluminum, copper) for interconnect compatibility. This composite material approach achieves both electrical performance and structural simplification.
Data Source
AI summary
A nonvolatile semiconductor storage device including a number of memory cells formed on a semiconductor substrate, each of the memory cells has a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode which are formed in sequence on the substrate. The gate electrode is structured such that at least first and second gate electrode layers are stacked. The dimension in the direction of gate length of the second gate electrode layer, which is formed on the first gate electrode layer, is smaller than the dimension in the direction of gate length of the first gate electrode layer.