3D-Stacked Gate Structure With Inner Spacer for Threshold Voltage Separation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in forming two different work-function metal layers for lower and upper nanosheet transistors in multi-stack semiconductor devices, particularly in achieving distinct threshold voltages for CMOS structures, is a significant manufacturing hurdle.
Innovation Solution
A multi-stack semiconductor device design incorporating an inner spacer between the lower and upper work-function metal layers, where the inner spacer protects the lower work-function metal layer during the formation of the upper work-function metal layer, allowing for the use of different materials for the two layers and enabling distinct threshold voltages for the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two different work-function metal layers are formed for lower and upper nanosheet transistors to achieve distinct threshold voltages, then the device functionality and threshold voltage differentiation are improved, but the manufacturing complexity and process difficulty increase
Solution Approach 1:
The gate structure is segmented into distinct lower and upper work-function metal layers with different materials (e.g., TiN for lower, TaN for upper), allowing independent control of threshold voltages for lower and upper nanosheet transistors. This segmentation enables the formation of complementary-metal-oxide transistor (CMOS) structures with opposite polarity transistors while maintaining separate processing control for each layer
Solution Approach 2:
An inner spacer structure is introduced as an intermediary element between the lower and upper work-function metal layers. This inner spacer serves as a protective barrier that prevents direct contact and potential contamination between the two metal layers during the epitaxial growth process, thereby simplifying the manufacturing process by eliminating the need for complex isolation techniques while enabling threshold voltage differentiation
2Manufacturing precision
If different materials are used for lower and upper work-function metal layers, then the threshold voltage control is improved, but the risk of material contamination and process defects increases
Solution Approach 1:
The inner spacer acts as a protective intermediary between the lower work-function metal layer (e.g., TiN) and the upper work-function metal layer (e.g., TaN). During the epitaxial growth process, this inner spacer prevents direct exposure of the lower metal layer to growth conditions that could cause contamination, thereby maintaining material purity and reducing process defects while enabling precise threshold voltage control through material selection
Solution Approach 2:
The inner spacer is formed in advance before the upper work-function metal layer is deposited. This preliminary action creates a protective barrier that prevents contamination of the lower metal layer during subsequent processing steps, ensuring that the different materials can be used without increasing the risk of material contamination
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E
AI summary
Provided is a multi-stack semiconductor device that includes: a lower field-effect transistor in which a lower channel structure (110) is surrounded by a lower gate structure including a lower gate dielectric layer (115D), a lower work-function metal layer (115F) and a lower gate metal pattern (115M); and an upper field-effect transistor in which an upper channel structure (120) is surrounded by an upper gate structure including an upper gate dielectric layer (125D), an upper work-function metal layer (125F) and an upper gate metal pattern (125M), wherein a channel width of the upper channel structure is smaller than a channel width of the lower channel structure, and wherein a replacement metal gate (RMG) inner spacer (200) is formed between the lower work-function metal layer and the upper work-function metal layer at regions where the lower channel structure is not vertically overlapped by the upper channel structure.