3D-Stacked Gate Isolation Structure for Short-Circuit Prevention

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Solution Overview

Problem

There is a risk of short circuits between the gate structures of transistors in 3D-stacked semiconductor devices due to their nanometer scale, which can lead to performance issues and reliability concerns.

Innovation Solution

The implementation of a middle isolation structure using two or more vertically-stacked semiconductor layers, such as silicon germanium (SiGe), to isolate the gate structures of the transistors, thereby preventing short circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the device size is reduced to nanometer scale to increase device density, then the productivity and device density are improved, but the risk of short circuit between gate structures increases

Engineering Contradiction:

Improvedevice densityVSAvoidshort circuit risk

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The isolation structure is divided into multiple segments: a first isolation structure between the first transistor and second transistor, and a second isolation structure between the second transistor and third transistor. This segmentation allows each isolation structure to be independently optimized for preventing short circuits while maintaining compact device spacing for high density.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Isolation structures are introduced as intermediary elements between adjacent transistors. These isolation structures include dielectric layers and conductive layers that physically separate and electrically isolate the gate structures, preventing short circuits while allowing the transistors to be positioned closely for high device density.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If isolation structures are added between transistors to prevent short circuits, then the reliability is improved, but the device complexity increases

Engineering Contradiction:

Improveisolation effectivenessVSAvoidstructure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The isolation structures serve multiple functions simultaneously: they provide electrical isolation between gate structures, act as spacers during fabrication processes, and define the spatial arrangement of transistors. This multi-functionality reduces the need for separate dedicated isolation components, thereby limiting the increase in device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The isolation structures are combined with other device features such as using the same dielectric layers for both isolation and gate oxide functions, and integrating conductive layers that serve both as isolation barriers and as interconnect elements. This merging approach prevents the isolation structures from being entirely separate additions that would increase complexity.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20250040242A13d-stacked semiconductor device including middle isolation structure and bspdn structure

Publication Date: 2025.01.30 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided is a semiconductor device which includes: a 1st source/drain region connected to a 1st channel structure which is controlled by a 1st gate structure; a 2nd source/drain region, above the 1st source/drain region, connected to a 2nd channel structure which is controlled by a 2nd gate structure; and a middle isolation structure between the 1st gate structure and the 2nd gate structure, wherein the middle isolation structure comprises two or more vertically-stacked semiconductor layers.