Stacked Gate Semiconductor Memory Device Contact Region Optimization
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Solution Overview
Problem
Conventional NAND type flash memory devices face increased chip area due to the expansion of the contact plug forming region, which is caused by the need to account for misalignment in photolithography, leading to inefficiencies in word line and contact plug arrangement.
Innovation Solution
The semiconductor memory device employs a stacked gate structure with a charge accumulation layer and a control gate, where the word lines are arranged such that their terminal portions are alternately located closer to the row decoder or the memory cell array, reducing the width of the contact region and allowing for more efficient placement of contact plugs, thereby minimizing chip area and improving processing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the contact plug forming region is expanded to account for misalignment in photolithography, then the reliability of word line and contact plug connection is improved, but the chip area increases
Solution Approach 1:
The patent applies asymmetry by arranging contact plugs in a non-uniform pattern where odd-numbered contact plugs are shifted in the first direction relative to even-numbered contact plugs. This asymmetric arrangement allows the contact plugs to alternately sandwich the first axis, creating a compact layout that reduces the overall contact region width while maintaining reliable connections despite photolithography misalignment.
Solution Approach 2:
The patent utilizes dimensional optimization by arranging contact plugs to alternately sandwich the first axis in the first direction. This alternating pattern in the first direction, combined with the orthogonal second direction, creates a two-dimensional optimization that reduces the width of the contact region in the second direction while maintaining adequate spacing for misalignment tolerance.
2Area of stationary object
If the word line width is reduced to the minimum processing dimension, then the chip area is reduced, but the manufacturing precision requirement increases due to photolithography misalignment
Solution Approach 1:
The patent applies preliminary action by pre-positioning contact plugs in an alternating asymmetric pattern before final photolithography processing. This predetermined arrangement creates built-in alignment margins that compensate for expected photolithography misalignment, allowing the word line width to be reduced to the minimum processing dimension without compromising connection reliability.
3Ease of manufacture
If contact plugs are arranged in a conventional uniform pattern, then the ease of manufacture is improved, but the chip area increases due to larger contact region width
Solution Approach 1:
The patent implements asymmetry in the contact plug arrangement where odd-numbered contact plugs are positioned at different locations compared to even-numbered contact plugs in the first direction. This asymmetric pattern reduces the overall width of the contact region in the second direction while maintaining a fabrication process that can be achieved through standard photolithography and etching techniques.
Data Source
AI summary
A semiconductor memory device includes memory cells, a memory cell array, a contact region, and first contact plugs. The memory cells include a control gate and a current path. The memory cells are arranged in the memory cell array in the first direction. The contact region is adjacent to the memory cell array in a second direction orthogonal to the first direction. A terminal portion on one end of the control gate is drawn onto the contact region from within the memory cell array. Each of the first contact plugs is formed on the control gate located in the contact region. The first contact plugs are located so as to alternately sandwich a first axis in the first direction.