3D-Stacked Gate Structure Using Poly-Si to Protect Work-Function Metal
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Solution Overview
Problem
The existing process of forming different work-function metal layers in multi-stack semiconductor devices is challenging due to the risk of damaging the lower work-function metal layer during the wet etching of the upper-stack nanosheet channel layers, especially when the lower and upper stack nanosheet channel layers have different channel widths, requiring additional complex patterning and deposition steps to protect the lower work-function metal layer.
Innovation Solution
The use of a polycrystalline silicon (poly-Si) structure as the lower gate electrode and a metal or metal compound as the upper gate electrode, with a gate inner spacer formed between the work-function metal layers at selected regions, and a poly-Si layer between the work-function metal layers at specific areas, to protect the lower work-function metal layer and facilitate the formation of distinct work-function metal layers for the lower and upper nanosheet transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wet etching is used to remove the work-function metal layer from upper-stack nanosheet channel layers, then the upper gate structure can be differentiated, but the lower work-function metal layer may be etched or damaged
Solution Approach 1:
A gate inner spacer is introduced as an intermediary protective layer between the lower and upper work-function metal layers. This spacer prevents the wet etchant from reaching and damaging the lower work-function metal layer while allowing selective removal of the upper work-function metal layer, thus enabling gate structure differentiation without compromising the integrity of the lower layer.
Solution Approach 2:
The gate structure is segmented into distinct regions with different work-function metal layers. The lower gate structure retains its work-function metal layer while the upper gate structure has it selectively removed, creating differentiated threshold voltages for lower and upper nanosheet transistors. This segmentation is achieved through selective etching processes guided by the gate inner spacer.
2Reliability
If additional patterning and deposition steps are added to protect the lower work-function metal layer, then the lower work-function metal layer can be protected from etching, but the manufacturing process becomes more complex
Solution Approach 1:
The gate inner spacer is formed in advance, before the selective removal of the upper work-function metal layer. This preliminary formation of the protective spacer simplifies the subsequent etching process by providing built-in protection, eliminating the need for additional complex patterning steps that would otherwise be required to protect the lower work-function metal layer.
3Ease of manufacture
If the same work-function metal layer is used for both lower and upper nanosheet transistors, then the manufacturing process is simpler, but distinct threshold voltages cannot be achieved
Solution Approach 1:
Different work-function metal layer configurations are applied to different regions of the device. The lower gate structure maintains a work-function metal layer for one threshold voltage, while the upper gate structure has the work-function metal layer selectively removed for a different threshold voltage. This local differentiation enables CMOS functionality with distinct transistor characteristics while building upon a unified initial structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents damage to the lower work-function metal layer during the etching process, simplifies the manufacturing steps, and allows for the formation of distinct threshold voltages for the lower and upper nanosheet transistors, enhancing the reliability and efficiency of the multi-stack semiconductor device production.
Implementation Method 1
the work-function metal layer formed on the lower-stack nanosheet channel layers (i.e., the lower work-function metal layer) may also be etched or damaged by the wet etching
Data Source
AI summary
Provided is a multi-stack semiconductor device that includes: a substrate; a lower field-effect transistor in which a lower channel structure is surrounded by a lower gate structure including a lower work-function metal layer and a lower gate electrode; and an upper field-effect transistor in which an upper channel structure is surrounded by an upper gate structure including an upper work-function metal layer and an upper gate electrode, wherein each of the lower gate electrode and the upper gate electrode includes a metal or a metal compound, and wherein the lower gate electrode comprises polycrystalline silicon (poly-Si) or poly-Si comprising a dopant, and the upper gate electrode comprises a metal or a metal compound.