Stacked Gate Semiconductor Isolation Using Room-Temperature SAM Deposition
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Solution Overview
Problem
Existing integration processes for vertically stacked complementary transistors face challenges such as high deposition temperatures exceeding the thermal stability of organic self-aligned monolayers, plasma exposure damaging SAM materials, and complications in selective deposition of high-k dielectric films, leading to difficulties in achieving efficient isolation and scaling of nanosheets in monolithic integration.
Innovation Solution
A monolithic integration approach that includes selective deposition of isolation dielectric at room temperature without plasma, using self-assembled monolayers to resist deposition, and isotropic etching to form split gates, ensuring electrical isolation of vertically stacked transistors while maintaining film quality and avoiding thermal degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-k dielectric films are deposited using conventional methods, then film quality and coverage are improved, but deposition temperatures exceed thermal stability of organic self-aligned monolayers and plasma exposure damages SAM materials
Solution Approach 1:
The patent changes the deposition temperature parameter from conventional high temperatures to room temperature, enabling the use of organic self-aligned monolayers as deposition masks without thermal damage. This parameter change resolves the contradiction by allowing high film quality through selective deposition while maintaining thermal stability of the SAM layer.
Solution Approach 2:
The patent introduces organic self-aligned monolayers as an intermediary layer that enables selective deposition. The SAM layer acts as a deposition mask that resists dielectric deposition on specific regions (such as gate electrodes), allowing precise film formation without plasma damage to underlying sensitive materials. This intermediary resolves the contradiction by providing a protective and selective interface.
2Manufacturing precision
If conventional plasma-based deposition is used, then dielectric film coverage is improved, but plasma exposure damages SAM materials
Solution Approach 1:
The organic self-aligned monolayer serves as a protective intermediary that prevents plasma from damaging underlying sensitive materials. The SAM layer is resistant to plasma exposure, allowing plasma-based deposition processes to be used without harming the gate electrodes or other temperature-sensitive components. This intermediary resolves the contradiction by absorbing the plasma exposure harm.
Solution Approach 2:
The patent uses a disposable organic monolayer that can be easily deposited and removed. This temporary layer provides plasma protection during deposition, then is selectively removed to reveal the precisely formed dielectric structures. The low-cost, easily removable nature of the SAM layer makes it ideal for this single-use protective function.
3Reliability
If selective deposition is implemented using SAM materials, then electrical isolation of stacked transistors is improved, but process complexity increases
Solution Approach 1:
The organic self-aligned monolayers perform multiple functions automatically: they self-assemble on specific surfaces, provide deposition resistance on gate electrodes, protect underlying materials from plasma damage, and can be selectively removed. This self-service capability reduces the need for additional complex process steps while achieving reliable electrical isolation between stacked transistors.
Solution Approach 2:
The SAM materials provide multiple functions simultaneously: surface modification, deposition masking, plasma protection, and selective etch resistance. This multi-functionality consolidates what would otherwise require multiple separate process steps into a single integrated approach, reducing overall process complexity while achieving reliable electrical isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables rapid implementation of stacked transistors with improved scalability and reduced manufacturing complexity, addressing the challenges of high-volume manufacturing readiness for complementary FET technology by 2028.
Implementation Method 1
a self-assembled monolayer (SAM), and the first lower WFM is not covered by the SAM. For example, the SAM can be configured to resist deposition of the isolation dielectric
Data Source
AI summary
Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a first lower semiconductor device having one or more first lower channels and first lower work function metal (WFM) covering the first lower channels, and a first upper semiconductor device stacked vertically over the first lower semiconductor device. The first upper semiconductor device can have one or more first upper channels and first upper WFM covering the first upper channels. The semiconductor structure can also include a monolayer formed on dielectric surfaces of the semiconductor structure, and an isolation dielectric deposited on the first lower WFM and between the first lower semiconductor device and the first upper semiconductor device to isolate the first lower semiconductor device from the first upper semiconductor device.