Stacked-Gate Transistors Eliminate Floating Node Contacts
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Solution Overview
Problem
Conventional stacked-FET devices with contacts to floating nodes experience parasitic resistance and increased capacitance, degrading device performance due to trench silicide and trench contacts on epitaxial material.
Innovation Solution
The structure eliminates contacts to floating nodes, maintaining contacts only to the VDD and GND nodes, utilizing multiple FET devices connected in series with epitaxial diffusion regions connected to supply and ground, and employing trench silicide and trench contact formation on source/drain regions of end FET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contacts are made to floating nodes in stacked-FET devices, then contact resistance is reduced, but parasitic capacitance increases and device performance degrades
Solution Approach 1:
The patent extracts and removes the harmful element (contacts to floating nodes) from the system. By eliminating trench silicide and trench contacts from floating nodes, the patent removes the source of parasitic capacitance while maintaining necessary contacts only at VDD and GND nodes, thus resolving the contradiction between contact resistance and parasitic capacitance.
Solution Approach 2:
The patent applies different contact strategies to different parts of the device: floating nodes are left without contacts (devoid of trench silicide and trench contacts) while VDD and GND nodes maintain proper contacts. This localized differentiation optimizes each region's function, reducing parasitic capacitance in critical areas while maintaining necessary electrical connections elsewhere.
2Reliability
If trench silicide and trench contacts are formed on epitaxial material, then electrical connection is improved, but parasitic resistance and capacitance increase
Solution Approach 1:
The patent removes trench silicide and trench contacts from epitaxial material in floating node regions, eliminating the harmful parasitic effects while preserving necessary electrical connections through alternative means at non-floating nodes.
Solution Approach 2:
The patent applies trench silicide and trench contacts selectively: present at VDD and GND nodes where electrical connection is needed, but absent from floating nodes where they would create parasitic effects. This localized application resolves the contradiction between connection quality and parasitic resistance.
3Adaptability or versatility
If multiple FET devices are connected in series with floating nodes, then device functionality is achieved, but contact resistance and capacitance accumulate
Solution Approach 1:
The patent extracts and eliminates contacts from floating nodes in series-connected FET stacks, removing the accumulating parasitic resistance and capacitance that would otherwise degrade device performance while maintaining the necessary series connection functionality.
Solution Approach 2:
The patent applies a differentiated contact strategy across the series-connected FETs: floating nodes are left contactless to minimize parasitic accumulation, while VDD and GND nodes maintain proper contacts. This local differentiation prevents the cumulative degradation that would occur with uniform contact application across all nodes.
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to stacked gate transistors and methods of manufacture. The structure includes a stacked gate structure having a plurality of transistors with at least one floating node and at least one node to either ground or a supply voltage, and a contact to either of the ground or supply voltage and the at least one floating node being devoid of any contact.