3D Stacked Gate Electrodes with Variable Thickness Pads
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Solution Overview
Problem
There is a need for semiconductor devices with increased degrees of integration to process large amounts of data efficiently, as existing devices face limitations in integrating semiconductor components effectively.
Innovation Solution
The semiconductor device features gate electrodes stacked perpendicularly on a substrate with channel holes penetrating through, gate pads of varying lengths and thicknesses, and contact plugs connected to these pads, including an etch-stop layer, to enhance integration and data processing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate electrodes are stacked perpendicularly to increase integration degree, then data processing capability is improved, but device structure complexity increases
Solution Approach 1:
The patent transitions from planar gate electrode arrangement to three-dimensional perpendicular stacking, enabling multiple gate electrodes to be arranged vertically along the channel length direction. This dimensional change increases the number of transistors per unit area and enhances data processing capability while managing structural complexity through systematic design
Solution Approach 2:
The channel region is divided into multiple segments by stacking gate electrodes perpendicularly along the channel length. Each gate electrode controls a specific segment of the channel, allowing independent control and enabling complex logic operations through combinations of segmented gate controls
2Reliability
If gate pads are extended by different lengths to connect to contact plugs, then electrical connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The gate pad structure implements local quality variation by having different pad thicknesses at different locations. The pad thickness is reduced in the contact region compared to the region connected to the gate electrode, optimizing both electrical connectivity and stress distribution while accommodating varying manufacturing tolerances across different zones
Solution Approach 2:
The patent changes the thickness parameter of the gate pad along its length, creating a gradient or stepped structure. This parameter variation allows the pad to satisfy different functional requirements: sufficient thickness for mechanical strength and electrical connectivity near the gate electrode, and reduced thickness for stress relief and better contact plug alignment in the contact region
3Stability of the object's composition
If gate pad thickness is reduced in contact regions, then stress distribution is improved, but structural strength decreases
Solution Approach 1:
The gate pad exhibits different thickness characteristics in different regions: the region connected to the gate electrode maintains sufficient thickness for structural strength, while the contact region has reduced thickness for optimized stress distribution. This local differentiation allows simultaneous satisfaction of strength and stress distribution requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for improved integration and data processing efficiency by optimizing the structure of gate electrodes and pads, enabling more effective data handling and storage in semiconductor devices.
Implementation Method 1
at least portions of the sacrificial layers in the pad region being oxidized to form oxide layers
Data Source
AI summary
A semiconductor device, including gate electrodes perpendicularly stacked on a substrate; channel holes extending perpendicularly to the substrate, the channel holes penetrating through the gate electrodes, the channel holes having a channel region; gate pads extended from the gate electrodes by different lengths; and contact plugs connected to the gate pads, at least a portion of the gate pads having a region having a thickness less than a thickness of the gate electrode connected to the at least a portion of the gate pads.