Stacked Gate Electrode Via Structure for Dense Semiconductor Integration
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration density and reliability, particularly in the formation of gate contacts and connections between gate electrodes.
Innovation Solution
The semiconductor device incorporates a design with a first and second gate electrode connected via a connection via on the lower surface of the second gate electrode, enhancing integration density and reliability by specific structural configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional gate contact formation methods are used, then manufacturing simplicity is maintained, but integration density and reliability are insufficient
Solution Approach 1:
The gate contact structure is segmented into multiple components: a gate contact extending into the gate capping pattern, a bonding layer, and a connection via extending into the second substrate. This segmentation allows each component to be optimized independently for reliability while managing complexity through modular design.
Solution Approach 2:
The connection via extends vertically into the second substrate, utilizing the third dimension to establish electrical connection between the gate electrode and the second active pattern. This vertical dimensionality change enables improved reliability without increasing lateral footprint, thus managing device complexity.
2Productivity
If integration density is increased through closer spacing of components, then device functionality is improved, but manufacturing precision requirements increase
Solution Approach 1:
The bonding layer acts as an intermediary between the gate capping pattern and the second substrate, providing a tolerant interface that facilitates alignment while enabling close spacing. This intermediary structure improves integration density without proportionally increasing manufacturing precision requirements.
Solution Approach 2:
The gate contact is nested within the gate capping pattern, and the connection via is nested within the second substrate, creating a compact hierarchical structure. This nesting approach maximizes integration density by efficiently utilizing vertical space while maintaining manufacturability.
3Area of stationary object
If connection via is formed closer to the active pattern, then area is reduced, but reliability may be compromised
Solution Approach 1:
The connection via is positioned at a specific location on the lower surface of the second gate electrode with local optimized properties. The via structure and its spacing are locally tailored to achieve the best balance between area reduction and connection reliability, rather than applying uniform design rules throughout.
Data Source
AI summary
A semiconductor device may include, a first substrate, a first active pattern on the first substrate and extending in a first direction, a first gate electrode on the first active pattern and extending in a second direction different from the first direction, a gate capping pattern on the first gate electrode, a gate contact extending into the gate capping pattern and electrically connected to the first gate electrode, a bonding layer on the gate capping pattern, a second substrate on the bonding layer, a second active pattern on the second substrate, wherein the second active pattern comprises a lower pattern and a sheet pattern on the lower pattern, a second gate electrode on the second active pattern and a connection via on the gate contact and electrically connected to each of the gate contact and the second gate electrode, wherein the connection via extends into the second substrate.