Face-to-Face Stacked IC Layout With Fewer Metal Routing Layers
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Solution Overview
Problem
The increasing complexity and density of integrated circuit chips due to numerous circuit components lead to higher manufacturing costs and design/layout complexity, primarily driven by the need for multiple metal layers for routing.
Innovation Solution
Implementing Wafer-on-Wafer (WoW) technology, where multiple circuit components are distributed across two integrated circuit chips stacked face-to-face, allowing for reduced metal layers by increasing the planar layout area of circuit blocks and sharing power/signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of circuit components in an integrated circuit chip is increased, then the functional capability is improved, but the routing complexity and number of metal layers increase
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture by bonding multiple semiconductor substrates together. This vertical stacking enables circuit components to be distributed across different layers, reducing the routing complexity and number of metal layers required within each individual substrate while maintaining the total functional capability.
Solution Approach 2:
The integrated circuit is divided into multiple independent semiconductor substrates, each containing a subset of the total circuit components. This segmentation allows each substrate to have fewer components and simpler routing, while the stacked configuration provides the necessary interconnections between substrates to achieve the overall system functionality.
2Adaptability or versatility
If the number of metal layers is increased to accommodate more circuit components, then the routing capability is improved, but the manufacturing cost increases
Solution Approach 1:
Instead of adding more metal layers within a single substrate to increase routing capability, the patent adds vertical dimensions by stacking multiple substrates. Each substrate requires fewer metal layers, reducing manufacturing complexity and cost, while the stacked configuration provides additional routing paths through inter-substrate connections.
3Quantity of substance
If the number of circuit components is increased, then the functional capability is improved, but the design and layout complexity increase
Solution Approach 1:
The design process is segmented across multiple substrates, with each substrate designed independently with fewer components. This reduces the design and layout complexity for each individual substrate while the overall system achieves high functional capability through the combination of stacked substrates.
Solution Approach 2:
The patent moves the design complexity from a two-dimensional plane to a three-dimensional stacked architecture. By distributing components vertically across multiple substrates, the design and layout complexity within each substrate is reduced, making the overall design more manageable despite the increased total number of components.
4Quantity of substance
If all circuit components are integrated into a single circuit, then the functional capability is maximized, but the planar layout area required increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple semiconductor substrates to accommodate all circuit components. This three-dimensional arrangement significantly reduces the planar layout area required compared to a single-substrate configuration, as components are distributed across multiple vertical layers rather than spread out in a single plane.
Data Source
AI summary
A semiconductor apparatus is provided. The semiconductor apparatus includes: a first circuit, including a first semiconductor substrate, a first group of circuit components formed on the first semiconductor substrate, and a first group of metal layers, wherein, the first group of circuit components are distributed to at least one circuit block, and traces for each circuit block are formed in at least some of the first group of metal layers; a second circuit, including a second semiconductor substrate, a second group of circuit components formed on the second semiconductor substrate, and a second group of metal layers, wherein, the second group of circuit components are distributed to at least one circuit block, and traces for each circuit block are formed in at least some of the second group of metal layers, and the first circuit and the second circuit being face-to-face stacked and bonded.