Stacked IC Via Layout for Separate Data and Control Paths
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Solution Overview
Problem
Existing stacked integrated circuits face challenges in efficiently transmitting data and control signals between stacked chips due to asymmetrical and complex via configurations, leading to inefficiencies in data transmission and signal integrity.
Innovation Solution
The proposed solution involves symmetrical through via configurations and asymmetrical input/output (IO) circuit arrangements relative to rotating axes, along with a front face to front face bonding structure, allowing for separate channels for data and control signals, and the use of chip flags and output control modules to manage chip identification and data output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If asymmetrical via configurations are used in stacked integrated circuits, then manufacturing flexibility is improved, but data transmission efficiency deteriorates due to complex signal paths
Solution Approach 1:
The patent applies asymmetry in reverse - it deliberately creates symmetrical via configurations where the second chip's vias are positioned to mirror the first chip's vias relative to their respective rotating axes. This symmetry ensures that data and control signals follow balanced, predictable paths through the stacked chips, improving signal integrity and transmission efficiency while maintaining manufacturing flexibility through the modular bonding approach.
2Adaptability or versatility
If complex via configurations are used to connect stacked chips, then connection versatility is improved, but signal integrity deteriorates due to irregular signal paths
Solution Approach 1:
The patent segments the via configurations into distinct symmetrical sets - a first through via set and a second through via set in the first chip, corresponding to a third through via set and a fourth through via set in the second chip. Each set is positioned symmetrically relative to its chip's rotating axis, creating organized, predictable signal paths that maintain signal integrity while providing versatile connectivity options.
Solution Approach 2:
The patent uses asymmetry strategically by positioning IO circuits asymmetrically within each chip while maintaining symmetrical via arrangements. The first and second IO circuits are disposed asymmetrically relative to the first rotating axis, and the third and fourth IO circuits are disposed asymmetrically relative to the second rotating axis. This combination allows versatile I/O functionality while the symmetrical vias ensure reliable signal transmission.
3Productivity
If separate channels for data and control signals are implemented, then data transmission efficiency is improved, but device complexity increases due to additional via sets and IO circuits
Solution Approach 1:
The patent achieves multi-functionality by having each symmetrical via set serve dual purposes - the first through via set and second through via set in the first chip, along with their corresponding vias in the second chip, collectively handle both data transmission and control signal routing. The symmetrical arrangement allows the same structural pattern to serve multiple functional channels, improving efficiency without proportionally increasing complexity.
Data Source
AI summary
A stacked integrated circuit includes a first chip including a first through via set and a second through via set that are disposed to be symmetrical to each other in relation to a first rotating axis and including a first input and output (IO) circuit and a second IO circuit that are disposed to be asymmetrical to each other in relation to the first rotating axis and a second chip including a third through via set and a fourth through via set that are disposed to be symmetrical to each other in relation to a second rotating axis and including a third IO circuit and a fourth IO circuit that are disposed to be asymmetrical to each other in relation to the second rotating axis, the second chip being rotated around the second rotating axis and stacked on the first chip.