Stacked Image Sensor Capacitors Layout Efficiency
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Solution Overview
Problem
Existing image sensors face challenges in achieving high dynamic range and efficient signal processing due to limitations in capacitor density and layout area, particularly with deep trench capacitors occupying significant silicon device area.
Innovation Solution
The implementation of a stacked image sensor architecture where deep trench capacitors are placed on a separate die, allowing for high capacitance without using layout area in the photodiode array, with each photodiode electrically coupled to one or more capacitors, and through silicon vias (TSVs) for interdie connections, enabling efficient signal processing and reduced noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If deep trench capacitors are placed in the photodiode array, then capacitance is provided for signal storage, but layout area is significantly occupied reducing pixel density
Solution Approach 1:
The patent moves capacitors from the 2D photodiode array plane to a 3D stacked architecture, placing capacitors on a separate die beneath or adjacent to the photodiode array. This vertical dimensionality change allows high capacitance values without consuming horizontal layout area in the pixel array, thereby increasing pixel density while maintaining signal storage capability.
Solution Approach 2:
The image sensor is segmented into separate functional dies: a photodiode array die for light detection and a separate die for housing capacitors and readout circuitry. This segmentation allows each component to be optimized independently and connected through vertical interconnects (TSVs), resolving the area-capacitance tradeoff by spatially separating storage functions from detection functions.
2Adaptability or versatility
If more capacitors are integrated in the photodiode array, then dynamic range is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
By segmenting the image sensor into separate dies with capacitors on a dedicated die, the patent simplifies the photodiode array design while maintaining high dynamic range capability. The complexity of capacitor integration is isolated to a separate manufacturing process, allowing standard photodiode fabrication without the complexity of in-pixel capacitor integration.
Solution Approach 2:
Through-silicon vias (TSVs) serve as intermediary vertical interconnects between the photodiode array die and the capacitor die. This intermediary connection method enables complex capacitor networks to support high dynamic range without increasing the complexity of the photodiode array itself, as the capacitor configuration can be optimized independently on the separate die.
3Productivity
If capacitors are placed on a separate die, then layout efficiency is improved, but interdie connections are required adding manufacturing steps
Solution Approach 1:
The patent employs vertical stacking with TSVs to connect dies, achieving high layout efficiency by utilizing the third dimension (vertical space) rather than expanding the horizontal footprint. While this adds interdie connection steps, the standardized TSV process enables efficient manufacturing through wafer-level bonding techniques, making the added complexity manageable for high-volume production.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves high capacitance density, reduces noise, and facilitates high dynamic range and global shutter image sensors with improved layout efficiency and signal processing capabilities.
Implementation Method 1
Image sensors convey information related to an image by communicating signals in response to incident electromagnetic radiation
Implementation Method 2
a second die including a second plurality of interconnects and a plurality of capacitors, each capacitor selected from the group consisting of deep trench capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and 3D stacked capacitors
Data Source
AI summary
Implementations of image sensors may include a first die including an image sensor array and a first plurality of interconnects where the image sensor array includes a plurality of photodiodes and a plurality of transfer gates. The image sensor array may also include a second die including a second plurality of interconnects and a plurality of capacitors, each capacitor selected from the group consisting of deep trench capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and 3D stacked capacitors. The first die may be coupled to the second die through the first plurality of interconnects and through the second plurality of interconnects. No more than eight photodiodes of the plurality of photodiodes of the first die may be electrically coupled with no more than four capacitors of the plurality of capacitors.