Stacked Image Sensor Pixel Layout for Low-Noise Conversion Gain
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Solution Overview
Problem
CMOS image sensors face challenges in achieving high conversion gain and low noise levels due to shared floating diffusion nodes among adjacent photodetectors, leading to saturation or excessive noise at different lighting conditions.
Innovation Solution
A two-chip structure is implemented, with a separate floating diffusion node for each photodetector pixel, where the dual conversion gain transistor is placed on a second chip, connected via a short wiring structure to minimize capacitance and noise, and includes a dual conversion gain transistor in series with the reset transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a shared floating diffusion node is used among adjacent photodetectors, then device complexity is reduced, but noise level increases and measurement precision deteriorates
Solution Approach 1:
The patent divides the image sensor into two separate chips: the first chip contains the photodetector array with individual floating diffusion nodes, while the second chip contains the readout circuitry. This segmentation allows each photodetector to have its own dedicated floating diffusion node, eliminating the noise and saturation problems caused by shared nodes, while keeping the overall device manageable through modular architecture.
2Measurement precision
If a separate floating diffusion node is provided for each photodetector, then noise level decreases and measurement precision improves, but device complexity increases
Solution Approach 1:
The patent transitions from a planar single-chip architecture to a three-dimensional stacked architecture with two chips. By moving vertically to another dimension, the patent can provide individual floating diffusion nodes for each photodetector on the first chip while placing the corresponding readout circuitry on the second chip, thereby reducing in-pixel capacitance and noise without increasing lateral complexity.
Solution Approach 2:
The patent introduces a bonding interface between two chips as an intermediary structure. This bonding layer serves as a mediator that connects the photodetector array on the first chip with the readout circuitry on the second chip, allowing separate floating diffusion nodes while managing the complexity through standardized inter-chip connections.
3Ease of manufacture
If wiring structure length is increased to connect floating diffusion nodes, then ease of manufacture improves, but capacitance increases and noise level worsens
Solution Approach 1:
By stacking the readout circuitry on a separate chip directly above or adjacent to the photodetector array, the patent minimizes the lateral wiring distance while still achieving the necessary electrical connections. The vertical stacking approach reduces the effective wiring length compared to lateral routing, thereby reducing capacitance and noise while maintaining manufacturability through standard bonding processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for high conversion gain with low noise, enabling effective image sensing across a wide range of lighting conditions, particularly improving low-light performance and reducing noise levels.
Implementation Method 1
An image sensor includes an array of photodetectors each comprising a photosensitive area operative as a transducer that converts light into electrical charges
Data Source
AI summary
An image sensor has floating diffusion nodes and transfer gates on a first chip and source followers, dual conversion gain (DCG) transistors, select gates, and reset gates on a second chip. The floating diffusion nodes on the first chip are non-shared so that there is one for each photodetector pixel. The capacitance of the floating diffusion node proves to be lower in this two-chip non-shared arrangement than is feasible in any single chip arrangement. The DCG transistor may be placed in series with the reset transistor so that the DCG transistor may be included in the pixel circuit without adding wiring to the floating diffusion node. The wiring that is included in the floating diffusion node may be kept substantially vertical with only a single short horizontal wire that provides a connection between the source follower gate electrode and the DCG transistor source.