Stacked Image Sensor With Variable Resistance Memory Buffering

The image sensor is divided into multiple separate chips: a first chip containing the photoelectric conversion layer and a second chip containing the variable resistance element and memory region. This segmentation allows each chip to be optimized for its specific function, improving photoelectric conversion efficiency while enabling complex signal processing capabilities that would be difficult to achieve in a single integrated chip.

The patent transitions from a planar single-chip architecture to a three-dimensional stacked multi-chip architecture. The first and second chips are vertically stacked and connected through bonding interfaces, utilizing the vertical dimension to increase functional density and enable both high photoelectric conversion efficiency and advanced signal processing without increasing the horizontal footprint.

By segmenting the image sensor into specialized first and second chips, each chip can be manufactured using optimized processes for its specific function. The first chip focuses on photoelectric conversion with appropriate layer structures, while the second chip implements memory and variable resistance elements, allowing independent manufacturing optimization before final stacking.

The patent introduces bonding pads and bonding interfaces as intermediary elements that facilitate the connection between the first and second chips. These intermediaries provide standardized interfaces for electrical and mechanical coupling, simplifying the stacking process and enabling modular manufacturing where chips can be produced separately and then assembled with controlled complexity.

The patent changes the fundamental parameter of memory implementation by using variable resistance elements (such as phase-change materials or resistive switching materials) instead of conventional transistor-based memory cells. This parameter change enables higher density memory storage with smaller footprint, as variable resistance elements can achieve multiple storage states in a compact structure, thereby increasing image buffering capacity while reducing device area.

The second chip employs composite material structures combining variable resistance elements with memory region materials to create a hybrid memory system. This composite approach integrates the advantages of different materials to achieve high-density storage with reduced area, providing sufficient image buffering capacity in a compact form factor that reduces overall device size.