Stacked CMOS Image Sensor Pixel Layout for Smaller Pixel Pitch
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Solution Overview
Problem
The challenge of reducing the pitch of pixels in CMOS image sensors is exacerbated by the presence of the second pixel transistor and its associated interconnects on the same semiconductor chip, which increases complexity and reduces design flexibility and available space, making it difficult to minimize pixel size.
Innovation Solution
By relocating the second pixel transistor to a separate semiconductor chip bonded to the first, the complexity of interconnect routing on the first chip is reduced, allowing for easier reduction in pixel pitch and increased design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the second pixel transistor and its interconnects are placed on the same semiconductor chip as the first pixel transistor, then the pixel can function with complete circuitry, but the device complexity and interconnect routing complexity increase, reducing design flexibility and available space
Solution Approach 1:
The pixel circuit is segmented across two separate semiconductor chips. The first pixel transistor is on a first semiconductor chip, while the second pixel transistor and its associated interconnects are on a second semiconductor chip. This segmentation reduces the interconnect routing complexity on each individual chip while maintaining complete pixel functionality through the bonding interface between chips.
Solution Approach 2:
The second pixel transistor and its interconnects are extracted from the first semiconductor chip and placed on a separate second semiconductor chip. This extraction removes the source of complexity and space consumption from the first chip, allowing for reduced pixel pitch and improved design flexibility while preserving the electrical connection through chip bonding.
2Reliability
If the second pixel transistor and interconnects are on the same chip, then the pixel circuit is complete, but the available space on the chip is reduced, making it difficult to minimize pixel size
Solution Approach 1:
By segmenting the pixel circuit components across two chips, the area required for each pixel on the first semiconductor chip is reduced. The second pixel transistor and its interconnects occupy space on the second chip instead, allowing for minimized pixel size on the first chip while maintaining complete circuit functionality through the bonding interface.
Solution Approach 2:
The solution moves from a two-dimensional planar integration on a single chip to a three-dimensional stacked configuration with two bonded chips. This dimensional transition allows the second pixel transistor and interconnects to occupy space on a different chip layer, effectively increasing the available area on the first chip for pixel elements and enabling smaller pixel sizes.
Data Source
AI summary
An integrated chip includes a photodetector, a transfer transistor, a first pixel transistor, a capacitor, a second pixel transistor, and a bonding structure. A first terminal of the transfer transistor is coupled to a first terminal of the photodetector. The first pixel transistor is on a first semiconductor chip. A first terminal of the first pixel transistor is coupled to a second terminal of the transfer transistor. The capacitor is on the first semiconductor chip. A first terminal of the capacitor is coupled to a second terminal of the first pixel transistor. The second pixel transistor is on a second semiconductor chip bonded to the first semiconductor chip. The bonding structure is at an interface where the first semiconductor chip and the second semiconductor chip are bonded together. The bonding structure couples the second terminal of the capacitor to the first terminal of the second pixel transistor.