Stacked CMOS Image Sensor Layout for Low-Light RTS Noise
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Solution Overview
Problem
Existing CMOS image sensors face challenges in achieving high signal-to-noise ratio (SNR) in low light conditions, leading to increased random telegraph signal (RTS) noise.
Innovation Solution
The image sensor structure includes a three-chip construction where the source follower transistor, row select transistor, and reset transistor are fabricated on a different semiconductor layer than the photodiode, allowing for maximization of the channel area of the source follower transistor by using different types of transistors or connecting multiple transistors in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source follower transistor is fabricated on the same semiconductor substrate as the photodiode, then the device structure is simpler, but the channel area of the source follower transistor is limited and RTS noise increases
Solution Approach 1:
The patent divides the image sensor into multiple semiconductor substrates: a first substrate containing the photodiode and transfer gate transistor, and a second substrate containing the source follower transistor. This segmentation allows each transistor to be optimized independently, with the source follower transistor achieving a larger channel area on the second substrate without being constrained by the photodiode layout on the first substrate, thereby reducing RTS noise while maintaining manageable device complexity through modular construction
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture by placing the source follower transistor on a separate substrate above or below the photodiode substrate. This dimensional change enables the source follower transistor to achieve a larger channel area without increasing the lateral footprint, effectively resolving the contradiction between noise performance and device structure complexity
2Reliability
If multiple transistors are connected in parallel to maximize channel area, then RTS noise is reduced, but the device area and manufacturing complexity increase
Solution Approach 1:
The patent utilizes the third dimension by fabricating the source follower transistor on a separate substrate, enabling the channel to extend vertically or in stacked configurations. This allows multiple transistor channels to be effectively combined in parallel without proportionally increasing the lateral device area, as the additional channel area is achieved through vertical stacking rather than lateral expansion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces RTS noise in low light conditions by enhancing the signal-to-noise ratio and maximizing the channel area of the source follower transistor.
Implementation Method 1
A CMOS image sensor typically includes an array of picture elements (pixels), which utilizes light-sensitive CMOS circuitry to convert photons into electrons. The light-sensitive CMOS circuitry typically may include a photodiode formed in a semiconductor substrate. As the photodiode is exposed to light, an electrical charge is induced in the photodiode.
Data Source
AI summary
An image sensor structure and methods of forming the same are provided. An image sensor structure according to the present disclosure includes a semiconductor substrate including a photodiode, a transfer gate transistor disposed over the semiconductor substrate and having a first channel area, a first dielectric layer disposed over the semiconductor substrate, a semiconductor layer disposed over the first dielectric layer, a source follower transistor disposed over the semiconductor layer and having a second channel area, a row select transistor disposed over the semiconductor layer and having a third channel area, and a reset transistor disposed over the semiconductor layer and having a fourth channel area. The second channel area is greater than the first channel area, the third channel area or the fourth channel area.